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Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 7440534 | Master-slave flip-flop, trigger flip-flop and counter A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-sl... | 10/21/2008 |
| 5572561 | Frequency dividing circuit A frequency dividing circuit includes a first inverter circuit supplied with a first frequency-divided signal, a second inverter circuit supplied with a second frequency-divided signal which has a complementary relationship to the first frequency-divided ... | 11/05/1996 |
| 5509040 | Frequency divider A frequency divider includes a transmission gate having input and output terminals and a gate terminal to which a single-phase clock signal is applied to turn off and off the transmission gate; an element having an input terminal connected to the output t... | 04/16/1996 |
| 5453707 | Polyphase clock generation circuit A single-phase clock and an output signal of a second delay circuit are inputted to a first NAND gate and a first NOR gate. The output signal of the first NAND gate is inputted to a gate of a first PMOS transistor of a first clock driver. The output signa... | 09/26/1995 |
| 5253279 | Semiconductor integrated circuit having a built-in programmable divider A semiconductor integrated circuit includes an input terminal provided for each of input terminals. The input circuit outputs either one of "HIGH" or "LOW" as a frequency dividing ratio setting signal when the corresponding input terminal is "HIGH" or "LO... | 10/12/1993 |
| 5249214 | Low skew CMOS clock divider A low-skew CMOS clock divider circuit for providing tracking of the divide-by-one and divide-by-two output signals obtained from a source of master clock pulses is fabricated using two matched flip-flops externally wired as divide-by-two devices. Coincide... | 09/28/1993 |
| 5175753 | Counter cell including a latch circuit, control circuit and a pull-up circuit A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked... | 12/29/1992 |
| 5163074 | Dynamic frequency divider circuit with capacitor in loop to achieve fifty percent duty cycle output An improved dynamic frequency divider circuit is disclosed. A DC voltage generating circuit (10) generates a DC voltage (Vcon) having a level the same as a threshold voltage of an inverter. A voltage application circuit (41) supplies a voltage (Vcon) to o... | 11/10/1992 |
| 5148050 | Variable frequency-dividing circuit One output signal of a D flip-flop circuit FF2 is fed via a wiring W1 back to an input terminal of a D flip-flop circuit FF1, while one output signal of a D flip-flop circuit FF3 is fed via a wiring W2 back to another input terminal of the D flip-flop cir... | 09/15/1992 |
| 5131018 | Counter circuit with two tri-state latches A counter circuit is disclosed. The circuit has a first tri-state inverter for receiving data bits and their components. It includes a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state ... | 07/14/1992 |
| 5111489 | Frequency-dividing circuit In a frequency-dividing circuit for producing an output having a frequency half that of its input, a pair of terminals of a latch circuit are connected to input terminals of a pair of amplify/delay means, and are also connected to receive through a pair o... | 05/05/1992 |
| 5003566 | Hyperfrequency circuit comprising a dynamic divide-by-two frequency divider circuit employing single interrupt FET, buffer and inverter in a loop A hyperfrequency dynamic divide-by-two frequency divider circuit includes an inverter stage A and a follower stage B, in which the output of the inverter stage is applied to the input of the follower stage via an interrupt transistor T1 which i... | 03/26/1991 |
| 4990796 | Tristable multivibrator Disclosed is a circuit which provides the controlled generation of tri-level digital signals utilizing Field Effect Transistors (FETs), as active elements. The stability of all three states is due to a unique feed-back technique, and utilization of the ga... | 02/05/1991 |
| 4953187 | High speed prescaler A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the... | 08/28/1990 |
| 4902909 | Flip-flop arrangement for a divide-by-2 frequency divider comprising master-slave type memory elements A flip-flop (40) for a divide-by-2 frequency divider having a first stage (50) formed by two master-slave-type memory elements (10a, 10b) each having a two-input NOR gate (20a, 20b), and by a second stage (60) with 2 NOR gates (61, 62) connected as an RS ... | 02/20/1990 |
| 4882505 | Fully synchronous half-frequency clock generator A clock generating circuit having at least one loop of at least two stages. Each stage consists of a pass transistor serially connected to an inverter. An inverter couples the end of the loop to its beginning. The gate electrodes of the transistors in the... | 11/21/1989 |
| 4860327 | Latch circuit constructed with MOS transistors and shift register using the latch circuits A first circuit is made up of a first clocked inverter and a first modified clocked inverter. A second circuit is made up of a second clocked inverter and a second modified clocked inverter. The first circuit has substantially the same circuit arrangement... | 08/22/1989 |
| 4856035 | CMOS binary up/down counter A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mo... | 08/08/1989 |
| 4759043 | CMOS binary counter A 1.2 μm CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens ... | 07/19/1988 |
| 4734597 | CMOS inverter chain A CMOS inverter chain includes the alternating series connection of N- and P-inverters. An N-inverter is a conventional type of CMOS inverter employing an N-intermediate transistor between both the P- and the N-transistor; a P-inverter, however, is a CMOS... | 03/29/1988 |
| 4733111 | Sequential-logic basic element in CMOS technology operating by a single clock signal The basic element provided by the invention carries out the basic logic functions of storage and/or transfer of the data applied at the input, typical of a latch. Two ways of embodiment of the basic element having active phase at the high and low level of... | 03/22/1988 |
| 4706266 | Dual mode-increment/decrement N-bit counter register A counter cell for counting either up or down by one or two includes a multiplexer section, an increment/decrement section, and a carry section. The multiplexer section is responsive to control signals and input carry signals for generating a count signal... | 11/10/1987 |
| 4700370 | High speed, low power, multi-bit, single edge-triggered, wraparound, binary counter A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technolog... | 10/13/1987 |
| 4698831 | CMOS incrementer cell suitable for high speed operations An incrementer cell includes an input section, an output section and a carry section. The input section is responsive to an input data signal and an input carry signal for generating an incremented output signal. The output section is coupled to the input... | 10/06/1987 |
| 4696020 | Digital circuit for frequency or pulse rate division The digital circuit is for receiving a master clock signal at a frequency te f on an input and delivering a rectangular shaped output signal at a lower frequency (M/N)f where M is an integer and N is an even integer greater than M. The circuit comprises a... | 09/22/1987 |
| 4646331 | Electronic static switched-latch frequency divider circuit with odd number counting capability An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latc... | 02/24/1987 |
| 4637039 | Frequency divider circuit arrangement In order to reduce the likelihood of incorrect states being transferred from one cross-coupled transistor pair to the next in a frequency divider which comprises at least two such pairs (6a, 7a and 8a, 9a) which are energized alternately by means of a swi... | 01/13/1987 |
| 4587664 | High speed frequency divider dividing pulse by a number obtained by dividing an odd number by two An 8.5 divider comprises a first and second 1/2 dividers to produce output pulses having phases different from each other by 90°, a first logic gate producing output pulses having a repetition frequency of a half of the input pulses, a third and fourth 1... | 05/06/1986 |
| 4587665 | Binary counter having buffer and coincidence circuits for the switched bistable stages thereof A binary counter consists of a plurality of unit stages each having a bistable circuit, a buffer circuit for generating an output corresponding to an output state of the bistable circuit, a switching circuit for supplying an output of the buffer circuit t... | 05/06/1986 |
| 4574386 | Dynamically operable two-phase logic circuits A dynamic two-phase circuit arrangement includes two dynamic switching circuits, each of which has an input stage, a non-inverting output stage and an inverting output stage. Two-phase control of the two dynamic switching circuits is effected by two drive... | 03/04/1986 |
| 4568842 | D-Latch circuit using CMOS transistors A latch circuit includes a CMOS inverter to which a logic signal is applied to the input through an input terminal, which inverter continues to supply an output signal to its output terminal; and first depletion type p and n-channel MOS transistors connec... | 02/04/1986 |
| 4513432 | Multiple self-contained logic gate counter circuit A multibit counter circuit uses a plurality of essentially identical stages which each have a feedback circuit, a flip-flop, and a carry circuit. Each of the stages is connected together in essentially the same way. A counter circuit of any desired bit ca... | 04/23/1985 |
| 4512029 | Non-volatile decade counter using Johnson code or equivalent This invention concerns counters. More specifically, it relates to a non-volatile counting decade, comprising five flipflops, the outputs of which represent the decimal contents of the decade in the Johnson code. In this code, no flipflop changes its state ... | 04/16/1985 |
| 4512030 | High speed presettable counter A high speed countdown counter (FIG. 7) capable of operation at up to 10 MHz is provided which comprises a number of stages each comprising a flip flop (134, 136; 144, 146; etc.), a preset data input (IN1, IN2, etc.), a carry input (N11, N10, etc.), a dat... | 04/16/1985 |
| 4509182 | Binary counter A binary counter consists of some unit stages having a first pair of coincident gates composed of a first and a second coincident gates, a first input terminal of each being cross-coupled with the other's output terminal, and a second pair of coincident g... | 04/02/1985 |
| 4450369 | Dynamic MESFET logic with voltage level shift circuit GaAs digital electronics uses mainly depletion mode MESFET technology. In typical circuits, negative voltage logic input signals are required while the output voltage is positive. To connect gates, level shifters are needed to shift the positive voltage o... | 05/22/1984 |
| 4395774 | Low power CMOS frequency divider Means are described for generating a pair of oscillator signals that will respectively drive P and N channel transistors in Class B. These signals are used to clock a synchronous inverter stage that will only change state during the appropriate time inter... | 07/26/1983 |
| 4394769 | Dual modulus counter having non-inverting feedback The ring counter of this invention is self-initializing and is operable at a clock frequency corresponding to four gate delays and comprises a plurality of master of slave flip-flops, in which this high speed capability is attained by using non-inverting ... | 07/19/1983 |
| 4389728 | Frequency divider A frequency divider for electric timepieces or the like comprising a first block composed of even clock controlled inverters connected in cascade, a second block composed of even clock controlled inverters connected cascade and a clock controlled signal c... | 06/21/1983 |
| 4322644 | Circuit arrangement for controlling the operating functions of a broadcast receiver A circuit arrangement for controlling the operating functions in a device such as a broadcast receiver, including an up/down counter associated with each operating function wherein a particular count corresponds to a certain setting of the operating funct... | 03/30/1982 |
