Class 377/119 - Using bistable regenerative trigger circuits

Subclass of Class 377 - Electrical pulse counters, pulse dividers, or shift registers: circuits and systems
Definition: Subject matter where each stage utilizes a device which,
No. of patents: 24
Last issue date: 01/04/2011

Number	Title	Issue Date
7864915	Low-power asynchronous counter and method Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of fli...	01/04/2011
7440534	Master-slave flip-flop, trigger flip-flop and counter A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-sl...	10/21/2008
7197104	Minimum gate delay edge counter An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycl...	03/27/2007
7119587	High frequency divider state correction circuit The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The r...	10/10/2006
7061284	High frequency divider state correction circuit with data path correction The present invention provides for state correction. A first flip flop coupled to a second flip flop. A state correction circuit coupled to the output of the second flip flop. A third flip flop is coupled to the output of the state correction circuit. A fourth flip ...	06/13/2006
6642758	Voltage, temperature, and process independent programmable phase shift for PLL A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional progra...	11/04/2003
6085343	Method for concurrent testing of on-chip circuitry and timing counters A testing method in which the stages in a multi-stage counter chain are tested sequentially. A counter chain is composed of two or more stages with the carry-out signal from each stage being coupled to the carry-in signal of a subsequent stage. Various ci...	07/04/2000
5946369	High-speed binary synchronous counter with precomputation of carry-independent terms An N-bit binary synchronous counter includes K counter stages, with each stage including N/K flip-flops or other suitable storage elements. A given one of the counter stages receives a carry-in signal generated by another counter stage or by a carry logic...	08/31/1999
5600695	Counter circuit having load function A counter circuit having a load function which is able to speedily yet stably perform counting operations no matter what kind of value has been loaded. The counter circuit having a load function performs counting operations in synchronization with an inpu...	02/04/1997
5432830	High speed counter for alternative up/down counting of pulse trains and method therefor An asynchronous counter includes a plurality of flip-flops, cascade connected to one another, the plurality of flip-flops serially receiving successive pulse trains having varying numbers of pulses per pulse train. Switching circuitry, coupled to the plur...	07/11/1995
5164970	Cascaded driver circuit A cascaded driver circuit has two or more stages connected to a common serial data signal line and a common clock pulse signal line. Each stage has a counter circuit for dividing the frequency of the clock pulse signal and an enable latch circuit for latc...	11/17/1992
5132642	PLL using asynchronously resettable divider to reduce lock time An asynchronously resettable counter/divider (25) in a phase-locked loop (PLL) for a frequency synthesizer (12) reduces the lock-up time for the PLL by resetting the resettable counter/divider when the phase difference between the output signal from a VCO...	07/21/1992
4975931	High speed programmable divider A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the...	12/04/1990
4902909	Flip-flop arrangement for a divide-by-2 frequency divider comprising master-slave type memory elements A flip-flop (40) for a divide-by-2 frequency divider having a first stage (50) formed by two master-slave-type memory elements (10a, 10b) each having a two-input NOR gate (20a, 20b), and by a second stage (60) with 2 NOR gates (61, 62) connected as an RS ...	02/20/1990
4839912	Switching circuit arrangement for monitoring a binary signal A circuit arrangement for monitoring a binary signal having at least one level shift within a characteristic waiting time, such circuit including two flip-flops which receive control pulses at intervals at least as long as the characteristic waiting time....	06/13/1989
4741005	Counter circuit having flip-flops for synchronizing carry signals between stages A multistage counter circuit comprising a plurality of counters connected in cascade, each providing a carry signal and having signal logic levels at an output of each stage inverted by main clock pulses and sub clock pulses, and means including a flip-fl...	04/26/1988
4575867	High speed programmable prescaler A high speed programmable prescaler has an input divider that divides an input stream of clock pulses by either 2 or upon command by 3. Connected to the input divider is a plurality of dividers that are electrically cascaded together from a first member t...	03/11/1986
4521898	Ripple counter circuit having reduced propagation delay A ripple counter circuit is provided that reduces propagation delay inherent in flip-flops, and therefore, reduces the current required. A first flip-flop has a clock input responsive to a clock signal and a D input connected to a Q output. A second flip-...	06/04/1985
4517474	Logic circuit building block and systems constructed from same A logic system which includes a plurality of identical logic circuit building blocks, each referred to as an M Circuit, is disclosed. The M Circuits are connected in a linear array of interconnected M Circuits including first through last M Circuits, the ...	05/14/1985
4509182	Binary counter A binary counter consists of some unit stages having a first pair of coincident gates composed of a first and a second coincident gates, a first input terminal of each being cross-coupled with the other's output terminal, and a second pair of coincident g...	04/02/1985
4438350	Logic circuit building block and systems constructed from same A logic circuit building block, referred to as an M Circuit, is provided which solves various problems of prior art logic circuit building blocks and binary logic systems. The M Circuit responds to transitions of a two level binary input signal to provide...	03/20/1984
4399549	Odd number frequency division with symmetrical output A method and apparatus is described for dividing a clock frequency by any odd number to obtain a symmetrical output. Generally, some dividers in a chain of divide-by-two dividers are designated as controlled dividers and others are designated as uncontrol...	08/16/1983
3970867	Synchronous counter/divider using only four NAND or NOR gates per bit A plural bit-stage synchronous counter/divider wherein each bit-stage comprises four multiple-input inverting gates in flip-flop configuration with the output of the first and second gates connected to one of the multiple inputs of the third and fourth ga...	07/20/1976
3943379	Symmetrical odd modulus frequency divider Logic circuit for dividing an input frequency symmetrically by an odd number without producing spurious transients....	03/09/1976

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Class 377/119 - Using bistable regenerative trigger circuits