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An armor with rollers is provided that enables a user to move in all positions by rolling on a hard and smooth surface while constantly varying his bearing points on the ground.
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| Number | Title | Issue Date |
| 8165263 | Counting circuit and address counter using the same A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal. Each of the first to fourth FFs receives a signal at a c... | 04/24/2012 |
| 8023614 | Counting circuit and address counter using the same A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fif... | 09/20/2011 |
| 7965809 | Counter circuit A counter circuit adding a first value indicated by a plurality of bits and a second value in response to a clock signal, a first part of the plurality of bits being lower order than a second part of the plurality of bits, the counter circuit including a first count... | 06/21/2011 |
| 7813468 | Counter circuit Reduction in power consumption of a counter circuit for continuous operation is demanded. Therefore, provided is a counter circuit including: a first counter of m bits for counting and storing a value of a predetermined bit width according to an input clock; a clock... | 10/12/2010 |
| 7760847 | Counting circuit and address counter using the same A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fif... | 07/20/2010 |
| 7746973 | Signal detection circuit A signal detection circuit comprising: a differential amplifier to which an output voltage of a detection coil of a magnetic sensor is to be applied; a comparator to output a digital signal being at one logic level in a period between two spike-shaped voltages adjac... | 06/29/2010 |
| 7702062 | Electronic sensor with optimized counting capacity Embodiments of the present disclosure relate to an electronic sensor including capture means producing a signals comprising x pulses during a given capture time, such that a′ | 04/20/2010 |
| 7432742 | System and method for detecting an edge of a data signal A system and method for detecting an edge of a data signal carried on an observability bus. In one embodiment, a first performance counter is connected to receive the data signal in order to assert a trigger signal in response to detecting an assertion of the data s... | 10/07/2008 |
| 7394886 | Semiconductor device with latency counter A latency counter of a semiconductor device comprises a single cyclic signal generator and a command delay circuit. The single cyclic signal generator cyclically produces 0-th to n-th base signals based on an internal clock signal. The command delay circuit comprise... | 07/01/2008 |
| 7203265 | Synchronous counting circuit A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to seque... | 04/10/2007 |
| 7197104 | Minimum gate delay edge counter An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycl... | 03/27/2007 |
| 7190756 | Hybrid counter with an asynchronous front end Integrated circuit counting apparatuses are described. More particularly, a hybrid counter (203) including an asynchronous counter (310) front end and a synchronous counter (311) back end is described. The asynchronous counter (310) inclu... | 03/13/2007 |
| 7145978 | High speed binary counter A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B0 and B1, and at least two AND gates for each higher order binary bit. The counter also includes an input fac... | 12/05/2006 |
| 7057427 | Power on reset circuit A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion... | 06/06/2006 |
| 7006149 | Video signal control circuit The delay circuit composed of plural flip-flops converts an input data into plural data 110-0˜110-n having delays of 1˜n clocks, which are inputted to the selector of the selector circuit. The counter counts the pixel number per one lin... | 02/28/2006 |
| 6956793 | Phase clock selector for generating a non-integer frequency division A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fract... | 10/18/2005 |
| 6952121 | Prescaling for dividing fast pulsed signal Circuits, devices and methods are provided for dividing a fast pulse signal by an integer M. A dual modulus prescaler receives input pulses, counts them, and generates one prescaled pulse for every Qth input pulse. Q is a division modulus, and has a different value ... | 10/04/2005 |
| 6898262 | Programmable controller An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle of an output pulse is output from the pulse dividing sect... | 05/24/2005 |
| 6892315 | Adjustable microcontroller wake-up scheme that calibrates a programmable delay value based on a measured delay An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to wake-up the second circuit in response to an input signal. The input signal generally comprises a programmable delay value. ... | 05/10/2005 |
| 6538523 | Multi-channel pulse width modulation apparatus and down counter When a PWM signal is generated by PWM generators which are provided for the number of channels, each PWM generator outputs the PWM start schedule data showing the timing of startup of the PWM signal to the CPU. When the number of PWM signals which start a... | 03/25/2003 |
| 6445760 | Partially-synchronous high-speed counter circuits Partially-synchronous and non-integer integrated circuit counters for dividing a high-speed reference clock signal with a selectable divisor have been provided. The circuits use a high-speed synchronous counter that cycles between the use of a selectable ... | 09/03/2002 |
| 6430250 | Rapid triggering digital timer The invention relates to a digital timer (20) comprising a binary counter (21) driven by a counting clock signal (Hc), the counter (21) presenting a stabilization time after each counting pulse, and means for delivering a detection signal (DS2) with a pre... | 08/06/2002 |
| 6377650 | Counter register monitor and update circuit for dual-clock system An improved counter register (30) and method of transferring data from a host data bus (29) controlled by a first clock source (BCLK) to the cycle timer (18) controlled by a second clock source (NCLK) which frees the host data bus (29) to perform other fu... | 04/23/2002 |
| 6085343 | Method for concurrent testing of on-chip circuitry and timing counters A testing method in which the stages in a multi-stage counter chain are tested sequentially. A counter chain is composed of two or more stages with the carry-out signal from each stage being coupled to the carry-in signal of a subsequent stage. Various ci... | 07/04/2000 |
| 5818895 | High-speed counter circuit A high-speed counter circuit comprising an input line for inputting a clock signal, at least two bit counters for generating a count value of at least two bits in response to the clock signal from the input line, at least one clock synchronizing circuit r... | 10/06/1998 |
| 5708453 | Ramp signal producing method, ramp signal producing apparatus, and liquid crystal drive/display apparatus In a ramp signal producing apparatus, a ramp signal is produced under low clock signal frequency in a compact circuit arrangement. Luminance control and a white balance control are carried out by the ramp signal in a liquid crystal display. The ramp signa... | 01/13/1998 |
| 5526393 | Synchronous counter A synchronous counter comprises one D flip-flop circuit for performing divide-by-2 frequency division of a clock signal CK, JK flip-flop circuits for, when input signals have HIGH levels (logical value 1), inverting the levels of the output signals in syn... | 06/11/1996 |
| 5526391 | N+1 frequency divider counter and method therefor An N+1 frequency divider counter (20) has a binary counter (22), ones detect circuitry (26), control logic (24), and an output flip-flop (28). The binary counter (22) counts from an initial value to a final value for each half of an output clock signal. I... | 06/11/1996 |
| 5249214 | Low skew CMOS clock divider A low-skew CMOS clock divider circuit for providing tracking of the divide-by-one and divide-by-two output signals obtained from a source of master clock pulses is fabricated using two matched flip-flops externally wired as divide-by-two devices. Coincide... | 09/28/1993 |
| 5224133 | Modular high speed counter employing edge-triggered code A high speed modular counter (100) utilizing a novel counting method in which the first bit changes with the frequency of the driving clock, and changes in the higher order bits are initiated one clock pulse after a "0" to "1" transition of the next lower... | 06/29/1993 |
| 5167031 | Variable frequency clock pulse generator for microcomputer A clock pulse generator for a one-chip microprocessor permits the microprocessor to be operated on two different power sources by effectively using a single source of clock pulses, a clock pulse divider and gate circuits to gate a specific sequence of pul... | 11/24/1992 |
| 5063578 | Digital logic circuits for frequency multiplication A digital logic circuit (100) is provided for multiplying, such as doubling, the frequency of an input clock pulse sequence of period T. The circuit in one embodiment includes complementarily clocked first and second chains of cascaded delay elements (12,... | 11/05/1991 |
| 5012497 | High speed frequency divider circuit A frequency divider receives a first frequency signal and at least one clock signal of a sub-multiple of the first frequency. The first frequency signal charges a storage terminal once each first frequency cycle and the sub-multiple frequency signal disch... | 04/30/1991 |
| 4951303 | High speed digital programmable frequency divider A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing a periodic input w... | 08/21/1990 |
| 4926451 | Timing controller for high-speed digital integrated circuit There is disclosed a digital integrated circuit device which has high-speed transistors of a selected type. A timing controller is incorporated in this device and performs timing control for an internal digital circuit. The timing controller includes a se... | 05/15/1990 |
| 4855683 | Digital phase locked loop with bounded jitter A digital phase locked loop operable over a wide dynamic range has jitter performance that is exactly bounded within predetermined limits. The phase locked loop includes an accumulator-type digital voltage controlled oscillator (201) which generates from ... | 08/08/1989 |
| 4821299 | Semiconductor integrated circuit device including shift register having substantially equalized wiring between stages thereof In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input ... | 04/11/1989 |
| 4748347 | Logic coincidence gate, triplet of logic gates and sequential logic circuit using this logic gate The invention pertains to programmable fast logic. The logic gate of the invention comprises two parallel-mounted inverters comprising one transistor and one saturable load. The second inverter is powered through a transistor, the electrode gate of which, link... | 05/31/1988 |
| 4692640 | Majority circuit comprising binary counter The majority circuit has an (n+1)/2-notation counter circuit comprising a plurality of cascade-connected binary counters. An odd number of n-bit serial data are counted by the counter circuit, and an output of the binary counter of the last stage is taken... | 09/08/1987 |
| 4596027 | Counter/divider apparatus A counter/divider apparatus employing an array of counters arranged in parallel. Each counter repeatedly counts through a sequence of a number of clock pulses. The number is different for each counter and the numbers are relatively prime numbers. The outp... | 06/17/1986 |
