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| Number | Title | Issue Date |
| 6975152 | Flip flop supporting glitchless operation on a one-hot bus and method A flip flop includes a master portion operable to latch at least one of an input signal and an inverted input signal. The flip flop also includes a slave portion operable to latch at least one of the signal latched by the master portion and an inverted signal latche... | 12/13/2005 |
| 6961402 | High-speed synchronous counters with reduced logic complexity Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinato... | 11/01/2005 |
| 6891915 | Calculating circuit for dividing a fixed-point signal 1. A calculating circuit for dividing a fixed-point input signal consisting of a sequence of n-bit-wide digital data values by an adjustable dividing factor 2a for generating a divided fixed-point output signal, comprising: a signal input (2... | 05/10/2005 |
| 6882699 | Monotonic up-counter in an integrated circuit An increasing monotonic counter over n bits formed as an integrated circuit, including an assembly of 2n+1−(n+2) irreversible counting cells distributed in at least n groups of 2p−1 counting cells, where p designates the group rank, and at ... | 04/19/2005 |
| 6324238 | Bit counter stage, particularly for memories A bit counter stage, particularly for memory addresses, including: a master storage circuit; a slave storage circuit which is connected to the master storage circuit; a circuit for enabling the transit of an external address in the master storage circuit;... | 11/27/2001 |
| 6297681 | Multi-cell delay generator device wherein the cells have transistor stacks and selective stack transistor bypasses A digital delay generator device is based on a series arrangement of cells, wherein each cell has a first input for receiving a single-phase clock signal, a second input for receiving a delayable signal for thereto imparting a cell delay, and an output fo... | 10/02/2001 |
| 6008678 | Three-phase master-slave flip-flop A master-slave flip-flop has two switches that control the flow of data into and through the master and slave stages. The switches are controlled by a three-phase clock signal that is designed to address the problem of data shoot-through. Implementations ... | 12/28/1999 |
| 5818895 | High-speed counter circuit A high-speed counter circuit comprising an input line for inputting a clock signal, at least two bit counters for generating a count value of at least two bits in response to the clock signal from the input line, at least one clock synchronizing circuit r... | 10/06/1998 |
| 5619157 | Synchronizing circuit with dynamic and static latch circuitry A synchronizing circuit including a plurality of latches, comprised of a first dynamic type through latch circuit and a second dynamic type through latch circuit between which is disposed a static type through latch circuit, the circuits connected in casc... | 04/08/1997 |
| 5572561 | Frequency dividing circuit A frequency dividing circuit includes a first inverter circuit supplied with a first frequency-divided signal, a second inverter circuit supplied with a second frequency-divided signal which has a complementary relationship to the first frequency-divided ... | 11/05/1996 |
| 5557649 | Circuit configuration for dividing a clock signal A circuit configuration being made by differential technology for dividing a clock signal with switchable divider ratios of 4/5 by emitter coupled logic, includes first, second and third series-connected flip-flops each having an output, a data input and ... | 09/17/1996 |
| 5509040 | Frequency divider A frequency divider includes a transmission gate having input and output terminals and a gate terminal to which a single-phase clock signal is applied to turn off and off the transmission gate; an element having an input terminal connected to the output t... | 04/16/1996 |
| 5463340 | Phase clocked latch having both parallel and shunt connected switches for transmission gates A general object of the present invention is to provide a latch of which demand is small. In a half-latch 101, control signals T2 and T2C which vary at late timings are applied to a main unit for data input (update) operation while control signals T1 and ... | 10/31/1995 |
| 5287394 | Fast counter with uniform delay structures A fast counter includes a clock generator (18), a control circuit (22), and a counting circuit (12). The counting circuit is formed of at least one uniform delay structure (12a, 12b) having a plurality of counter bit cells (58, 60). The uniform delay stru... | 02/15/1994 |
| 5227674 | Semiconductor integrated circuit device A flip-flop circuit includes a data input terminal, a data output terminal, a memory circuit and a bypass circuit having a shorter delay time than that of the memory circuit. The memory circuit and the bypass circuit are connected in parallel between the ... | 07/13/1993 |
| 5175753 | Counter cell including a latch circuit, control circuit and a pull-up circuit A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked... | 12/29/1992 |
| 5163074 | Dynamic frequency divider circuit with capacitor in loop to achieve fifty percent duty cycle output An improved dynamic frequency divider circuit is disclosed. A DC voltage generating circuit (10) generates a DC voltage (Vcon) having a level the same as a threshold voltage of an inverter. A voltage application circuit (41) supplies a voltage (Vcon) to o... | 11/10/1992 |
| 5159616 | CMOS shift register with complementary refresh pass gates and buffer The improved CMOS shift register consists of a series of alternating PMOS and NMOS pass gates driven by a single clock signal. Each gate consists of either one or more PMOS transistor(s), or one or more NMOS transistor(s). When the clock signal goes low, ... | 10/27/1992 |
| 5131018 | Counter circuit with two tri-state latches A counter circuit is disclosed. The circuit has a first tri-state inverter for receiving data bits and their components. It includes a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state ... | 07/14/1992 |
| 5128974 | Shift register apparatus with improved clock supply A shift register apparatus comprising unit registers, clocks and gates. Only when data input to the apparatus is significant enough to shift the state of the unit registers, is the clock signal supplied selectively to the unit register of the applicable s... | 07/07/1992 |
| 5103116 | CMOS single phase registers A CMOS single phase register includes two pairs of cross coupled CMOS inverters connected together by transistor switches. The first pair of cross-coupled CMOS inverters is connected to a complementary pair of data inputs through a first pair of transisto... | 04/07/1992 |
| 5036217 | High-speed low-power flip-flop A master-slave flip-flop having a first bistable cell and a control circuit coupled to that first cell for changing the binary state of the cell in response to a set of complementary data inputs and a clock signal. The slave portion of the flip-flop inclu... | 07/30/1991 |
| 5023893 | Two phase non-overlapping clock counter circuit to be used in an integrated circuit An improved high speed two phase clock counter is disclosed. The counter includes a plurality of counter cells coupled to a transition pattern recognizer. Through the use of these elements a counter is provided that overcomes the power consumption and siz... | 06/11/1991 |
| 5012497 | High speed frequency divider circuit A frequency divider receives a first frequency signal and at least one clock signal of a sub-multiple of the first frequency. The first frequency signal charges a storage terminal once each first frequency cycle and the sub-multiple frequency signal disch... | 04/30/1991 |
| 5003566 | Hyperfrequency circuit comprising a dynamic divide-by-two frequency divider circuit employing single interrupt FET, buffer and inverter in a loop A hyperfrequency dynamic divide-by-two frequency divider circuit includes an inverter stage A and a follower stage B, in which the output of the inverter stage is applied to the input of the follower stage via an interrupt transistor T1 which i... | 03/26/1991 |
| 4988896 | High speed CMOS latch without pass-gates A high performance latch circuit having complemented isolation means that selectively maintain the state of the latch at a given logic state or input a new logic state thereto. The latch is made up of several legs of series connected translators, the legs... | 01/29/1991 |
| 4982414 | Abbreviated incrementer circuit An incrementer circuit includes a plurality of input terminals for receiving an address data, having a plurality of bits, to be incremented, a carry signal generating unit for generating a carry signal for each bit of the address data and a plurality of o... | 01/01/1991 |
| 4974241 | Counter employing exclusive NOR gate and latches in combination The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flo... | 11/27/1990 |
| 4953187 | High speed prescaler A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the... | 08/28/1990 |
| 4856035 | CMOS binary up/down counter A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mo... | 08/08/1989 |
| 4843254 | Master-slave flip-flop circuit with three phase clocking A master-slave flip-flop circuit includes a master circuit switching element controlled by a first clock signal for controlling transfer of data from an input terminal to a master circuit data holding element which holds data transferred through the maste... | 06/27/1989 |
| 4837465 | Single rail CMOS register array and sense amplifier circuit therefor A storage cell and a sense amplifier for use in a register or other memory in an integrated circuit. The storage cell has single-rail input and output, thereby eliminating the necessity of differential input lines and access transistors. The cell also has... | 06/06/1989 |
| 4820939 | Finite metastable time synchronizer A synchronizer circuit having a predictable and finite metastable time, and thereby a finite sample interval, resulting in the minimization of the probability of errors in asynchronous information transfer.... | 04/11/1989 |
| 4785204 | Coincidence element and a data transmission path A coincidence element responsive to a plurality of input signals for outputting the level of the input signals when said plurality of input signals coincide with each other includes, a serial connection of a first electrically conductive type and a second... | 11/15/1988 |
| 4759043 | CMOS binary counter A 1.2 μm CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens ... | 07/19/1988 |
| 4733111 | Sequential-logic basic element in CMOS technology operating by a single clock signal The basic element provided by the invention carries out the basic logic functions of storage and/or transfer of the data applied at the input, typical of a latch. Two ways of embodiment of the basic element having active phase at the high and low level of... | 03/22/1988 |
| 4706266 | Dual mode-increment/decrement N-bit counter register A counter cell for counting either up or down by one or two includes a multiplexer section, an increment/decrement section, and a carry section. The multiplexer section is responsive to control signals and input carry signals for generating a count signal... | 11/10/1987 |
| 4705965 | Interference free D-type flip-flop An electronic D-type flipflop includes two storage elements and two transmission gates wherein each gate includes only one MOS transistor. In the first gate the MOS transistor is of a first conductivity type and it is of a second conductivity type in the ... | 11/10/1987 |
| 4703200 | Static bistable flip-flop circuit obtained by utilizing CMOS technology A static bistable flip-flop circuit using CMOS technology. The flip-flop reduces the number of CMOS transistors by not using two complimentary transistors in parallel for certain switches. This reduces the risk of transparency which is inherent with conve... | 10/27/1987 |
| 4700370 | High speed, low power, multi-bit, single edge-triggered, wraparound, binary counter A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technolog... | 10/13/1987 |
