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| Number | Title | Issue Date |
| 7359475 | Counter circuit and semiconductor device containing the same A counter circuit includes a counter section having flip-flops of a plurality of stages. The flip-flops from a first stage to an (N-1)th (N is an integer more than 2) stage synchronously count a clock signal. A mask circuit section controls supply of the ... | 04/15/2008 |
| 7342425 | Method and apparatus for a symmetrical odd-number clock divider A method and apparatus for dividing the frequency of an input clock signal by an odd integer is disclosed. The output of two asymmetrical clock dividers may be combined to produce a divided clock signal having a symmetrical waveform. Finite state machines may be use... | 03/11/2008 |
| 7315191 | Digital storage element architecture comprising dual scan clocks and reset functionality A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first tran... | 01/01/2008 |
| 7151810 | Data and clock synchronization in multi-channel communications A clock signal is generated by receiving an input clock signal having an input clock signal frequency, dividing the input clock signal frequency by a selected number to produce a lower frequency output clock signal, and shifting the phase of the output clock signal.... | 12/19/2006 |
| 7149275 | Integrated circuit and method of implementing a counter in an integrated circuit An integrated circuit, such as a programmable logic device, implements a single bit transition counter in logic. The counter preferably comprises a first stage receiving a clock signal having a first clock rate and generating a least significant bit in a count. A pl... | 12/12/2006 |
| 7145978 | High speed binary counter A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B0 and B1, and at least two AND gates for each higher order binary bit. The counter also includes an input fac... | 12/05/2006 |
| 7123679 | Counter having improved counting speed A counter having enhanced counting speed is provided. The counter includes first through N-th output signal generators. The first output signal generator responds to a clock signal and outputs a first output signal in which a low level and a high level are output on... | 10/17/2006 |
| 7092480 | High-speed synchronous counters with reduced logic complexity Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinato... | 08/15/2006 |
| 7003067 | High-speed synchronous counters with reduced logic complexity Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinato... | 02/21/2006 |
| 6970025 | Programmable frequency divider Various apparatus and method embodiments are disclosed. One apparatus embodiment, among others, comprises a frequency divider configured to provide an output signal having a period equal to a period of a clock signal multiplied by a programming division ratio, the f... | 11/29/2005 |
| 6961402 | High-speed synchronous counters with reduced logic complexity Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinato... | 11/01/2005 |
| 6947077 | Fast and accurate adjustment of gain and exposure time for image sensors A proportional counting circuit generates count values for use in variably adjusting gain and exposure time of an image sensor array. The count values are adjusted in proportion to the current count value. This technique allows for fast and accurate adjustment of ga... | 09/20/2005 |
| 6937688 | State machine, counter and related method for gating redundant triggering clocks according to initial state A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to gen... | 08/30/2005 |
| 6882699 | Monotonic up-counter in an integrated circuit An increasing monotonic counter over n bits formed as an integrated circuit, including an assembly of 2n+1ā(n+2) irreversible counting cells distributed in at least n groups of 2pā1 counting cells, where p designates the group rank, and at ... | 04/19/2005 |
| 6839399 | Programmable counter with half-integral steps This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the fir... | 01/04/2005 |
| 6661864 | Counter circuit for detecting erroneous operation and recovering to normal operation by itself A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input ... | 12/09/2003 |
| 6535569 | Synchronous counter A synchronous counter includes at least three or more flip-flops having a chain structure, and at least two or more 2-input EXOR gates interposed in the chain structure. The number of stages of gates interposed between the output of one among the flip-flo... | 03/18/2003 |
| 6501816 | Fully programmable multimodulus prescaler The present invention is a method and system for a fully programmable modulus pre-scaler. In one embodiment, the pre-scaler is a cascade of fully programmable divide-by-2/3 sections. A fully programmable divide-by-2/3 section includes a state machine and ... | 12/31/2002 |
| 6470064 | Extended length counter chains in FPGA logic A synchronous counter, the inventive counter is synchronized to a clock, e.g., a master clock of an FPGA, and includes a first counter that increments in response to the master clock, a resynchronizer that receives counter bits from the first counter and,... | 10/22/2002 |
| 6269138 | Low power counters A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line includes a number of counter blocks, corresponding to the number of bits of the counter, connected in series. The low power counter blocks in... | 07/31/2001 |
| 6101233 | Counter circuit Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to outpu... | 08/08/2000 |
| 6091794 | Fast synchronous counter A synchronous counter circuit having a plurality of bit counting stages, each corresponding to a bit position for representing counts, from a least significant bit to a most significant bit. Each bit counting stage includes a flip-flip circuit and a synch... | 07/18/2000 |
| 6078637 | Address counter test mode for memory device A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit.... | 06/20/2000 |
| 6031887 | High-speed binary synchronous counter An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first ... | 02/29/2000 |
| 6026140 | Low power programmable ripple counter A ripple counter becomes programmable by use of intervening circuitry selectively inhibiting state transitions according to an initial programming step. The illustrated embodiment of a programmable ripple counter includes a forward chain of count register... | 02/15/2000 |
| 5960052 | Low power scannable counter A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of t... | 09/28/1999 |
| 5946369 | High-speed binary synchronous counter with precomputation of carry-independent terms An N-bit binary synchronous counter includes K counter stages, with each stage including N/K flip-flops or other suitable storage elements. A given one of the counter stages receives a carry-in signal generated by another counter stage or by a carry logic... | 08/31/1999 |
| 5943386 | High-speed synchronous counter circuitry Digital counter register stages are constructed as two-to-one mux registers, each employing a multiplexer stage having first, second, and third inputs and an output connected to the switching signal input of a D-type flip-flop, whose Q output comprises a ... | 08/24/1999 |
| 5818895 | High-speed counter circuit A high-speed counter circuit comprising an input line for inputting a clock signal, at least two bit counters for generating a count value of at least two bits in response to the clock signal from the input line, at least one clock synchronizing circuit r... | 10/06/1998 |
| 5799053 | High-speed predecoding address counter circuit A high-speed predecoding address counter circuit comprising at least three tetrad counters connected in series, each for inputting an external 4-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific... | 08/25/1998 |
| 5754615 | Fast programmable divider This invention relates to a programmable frequency divider that includes a plurality of flip-flops that are clocked at a frequency to be divided. The plurality of flip-flops is operatively arranged to allow the connection in a ring of a predetermined numb... | 05/19/1998 |
| 5600695 | Counter circuit having load function A counter circuit having a load function which is able to speedily yet stably perform counting operations no matter what kind of value has been loaded. The counter circuit having a load function performs counting operations in synchronization with an inpu... | 02/04/1997 |
| 5559844 | Binary counter with sped-up ripple carry A binary counter or binary-coded-arithmetic counter uses local look-ahead to speed up ripple carry propagation. A succession of counter stages therein can be identified by respective consecutive ordinal numbers assigned in accordance with the order of car... | 09/24/1996 |
| 5526393 | Synchronous counter A synchronous counter comprises one D flip-flop circuit for performing divide-by-2 frequency division of a clock signal CK, JK flip-flop circuits for, when input signals have HIGH levels (logical value 1), inverting the levels of the output signals in syn... | 06/11/1996 |
| 5469485 | Frequency divider A frequency divider, constituted by N divide-by-two binaries, comprises logic circuits that enable the generation of a signal of the end of the frequency division by means of the change in state of the most significant bit generated by the Nth order divid... | 11/21/1995 |
| 5398270 | Data coincidence detecting circuit A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, res... | 03/14/1995 |
| 5361289 | Synchronous counter circuit having a plurality of cascade-connected counters A synchronous counter circuit comprises first and second counting circuits and a latch circuit. Each of the first and second counting circuits includes a clock terminal for receiving a clock signal, an enable terminal for receiving an enable signal, a cou... | 11/01/1994 |
| 5339343 | Counter circuit with or gates interconnecting stages to provide alternate testing of odd and even stages during test mode A counter circuit includes a plurality of one-bit counters connected in series. The counter circuit includes first and second input terminals which are supplied with a predetermined signal, respectively, in an operational test mode. The counter circuit fu... | 08/16/1994 |
| 5331681 | Function adjustable signal processing device A signal processing device is provided with a plurality of signal processing circuits which are integrated on a monolithic semiconductor chip and which execute a plurality of predetermined signal processing stages. Signal input terminals are connected wit... | 07/19/1994 |
| 5233638 | Timer input control circuit and counter control circuit A circuit having a delay circuit provided with a gate for converting the output signal of an SR flip-flop into a signal with a delay equal to or more than the clock pulse width enough for count operation and leading the logical addition between the signal... | 08/03/1993 |