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| Number | Title | Issue Date |
| 7359475 | Counter circuit and semiconductor device containing the same A counter circuit includes a counter section having flip-flops of a plurality of stages. The flip-flops from a first stage to an (N-1)th (N is an integer more than 2) stage synchronously count a clock signal. A mask circuit section controls supply of the ... | 04/15/2008 |
| 7180349 | Frequency divider system A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which op... | 02/20/2007 |
| 7145978 | High speed binary counter A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B0 and B1, and at least two AND gates for each higher order binary bit. The counter also includes an input fac... | 12/05/2006 |
| 6992513 | Frequency divider system A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which op... | 01/31/2006 |
| 6891915 | Calculating circuit for dividing a fixed-point signal 1. A calculating circuit for dividing a fixed-point input signal consisting of a sequence of n-bit-wide digital data values by an adjustable dividing factor 2a for generating a divided fixed-point output signal, comprising: a signal input (2... | 05/10/2005 |
| 6795520 | High speed digital counters A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch. ... | 09/21/2004 |
| 6735653 | Bus bandwidth consumption profiler A bus bandwidth consumption profiler for measuring and reporting bus cycle utilization in a system having multiple bus masters, including master counters paired with the masters to count cycles of bus ownership, and a realtime counter to count elapsed cycles between... | 05/11/2004 |
| 5946369 | High-speed binary synchronous counter with precomputation of carry-independent terms An N-bit binary synchronous counter includes K counter stages, with each stage including N/K flip-flops or other suitable storage elements. A given one of the counter stages receives a carry-in signal generated by another counter stage or by a carry logic... | 08/31/1999 |
| 5754616 | Two-phase counter circuit A counter operated on the 2-phase clock which divides a lag time occurring in shift circuits into two parts, one being on the basis of a first clock and the other being on the basis of a second clock, the lag time in each part being independently accumula... | 05/19/1998 |
| 5729686 | Method for initializing a network having a plurality of network subscribers capable of acting as masters A method for initializing a network having a plurality of network subscribers being capable of acting as masters, includes assigning the master function to the network subscriber being capable of acting as a master that is turned on first. In the event of... | 03/17/1998 |
| 5233638 | Timer input control circuit and counter control circuit A circuit having a delay circuit provided with a gate for converting the output signal of an SR flip-flop into a signal with a delay equal to or more than the clock pulse width enough for count operation and leading the logical addition between the signal... | 08/03/1993 |
| 5230014 | Self-counting shift register A shift count confirmation shift register capable of receiving and storing logic values and sequentially providing representations thereof at the storage register output, as well as providing a shift complete signal at a confirmation signal output upon th... | 07/20/1993 |
| 5172400 | Frequency divider employing multiple stages of master/slave flip-flops A frequency divider includes at least three master-slave flip-flops which are connected to each other in stages, each stage including a master flip-flop and a slave flip-flop, to construct a 1/N frequency divider. At least two outputs whose periods are th... | 12/15/1992 |
| 5012130 | Small area and low current drain frequency divider cell for integrated circuits A pair of control transistors and a pair of storage transistors have their collectors coupled to a current source. The emitters of the storage transistors are grounded and the emitters of the control transistors are coupled to the bases of the storage tra... | 04/30/1991 |
| 5008905 | Universal shift register employing a matrix of transmission gates A universal shift register (200) utilizes a matrix (236-251) of high speed transmission gates to effect the various modes of register data manipulation in place of conventional operating mode selection logic gate elements. The shift register additionally ... | 04/16/1991 |
| 4799040 | Data conversion circuit A data conversion circuit is constructed in such a manner that a plurality of flip-flop series, each including tandem connected master/slave flip-flops, are provided and driven by plural phase numbers of clock signals which have no overlap therebetween, s... | 01/17/1989 |
| 4785297 | Driver circuit for matrix type display device A drive circuit for producing scanning pulses to successively select row or column conductors of a matrix display device of the type having an active element provided for each display element in the matrix, the drive circuit comprising a shift register ma... | 11/15/1988 |
| 4746915 | Drive circuit for matrix display device A drive circuit for sequentially driving electrodes of a matrix display device such as a liquid crystal display panel comprises a shift register divided into a plurality of groups of shift register stages and means for selectively applying a first clock s... | 05/24/1988 |
| 4741006 | Up/down counter device with reduced number of discrete circuit elements An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a ... | 04/26/1988 |
| 4741005 | Counter circuit having flip-flops for synchronizing carry signals between stages A multistage counter circuit comprising a plurality of counters connected in cascade, each providing a carry signal and having signal logic levels at an output of each stage inverted by main clock pulses and sub clock pulses, and means including a flip-fl... | 04/26/1988 |
| 4646331 | Electronic static switched-latch frequency divider circuit with odd number counting capability An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latc... | 02/24/1987 |
| 4601049 | Integrable semiconductor circuit for a frequency divider An integrable semiconductor circuit for a multi-stage frequency divider having a number of master-slave flip-flop cells constructed in current mode logic forming the individual divider stages which are connected in series to a supply voltage and which are... | 07/15/1986 |
| 4521897 | Apparatus for synchronizing the operation of master and slave counters A master and a slave counter have their outputs coupled to an exclusive OR gate which in turn, supplies the D input of a flip-flop. Clock pulses are coupled to the slave counter through an AND gate which is enabled by the Q output of the flip-flop. Clock ... | 06/04/1985 |
| 4493095 | Counter having a plurality of cascaded flip-flops An improved counter wherein consecutively cascaded flip-flops of the prior art are divided into two groups. A first detector produces a first signal in response to a predetermined set of flip-flop states of the first group. A second detector produces a se... | 01/08/1985 |
| 4464774 | High speed counter circuit There is shown and described a new and unique counter mechanism or circuit which includes feedback latches, in cascade, and which monitors a "carry-in" signal which selectively causes the latch to toggle. When the contents of the latch is a binary 1, the ... | 08/07/1984 |
| 4449104 | Circuit for controlling the output level of an electronic device Signal level control for an amplifier or the like is provided by a binary counter which counts upward when first operated, and which thereafter counts up and down if continually operated. If the operated counter is stopped after counting up, it counts up ... | 05/15/1984 |
| 4366394 | Divide by three clock divider with symmetrical output A flip-flop receives clock pulses of frequency F and is alternately set and reset on alternate inverted third clock pulse edges by logic responsive to the clock pulses and to the output of the flip-flop. The logic includes a second flip-flop and a pair of... | 12/28/1982 |
| 4357546 | Integrated frequency divider circuit A frequency divider circuit realized by means of two piled bistable transistor pairs, the signal, whose frequency is to be divided, being applied in phase to the emitters of the lower transistor pair and in phase opposition to the auxiliary emitters of th... | 11/02/1982 |
| 4132887 | Counting system A fuel pump register with pairs of oppositely facing volume and cost counters, conventional reset means for resetting the counter wheels to zero between fluid deliveries, the volume counters being indexed in a conventional manner for registering the volum... | 01/02/1979 |
| 3993918 | Integrated circuits A master/slave bistable arrangement which operates on current levels rather than voltage levels and with a single input of clock pulses. There are different bias current levels which are advantageously supplied by multi-layer current injection structures ... | 11/23/1976 |
| 3943379 | Symmetrical odd modulus frequency divider Logic circuit for dividing an input frequency symmetrically by an odd number without producing spurious transients.... | 03/09/1976 |