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"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 7369432 | Method for implementing a counter in a memory with increased memory efficiency A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the fir... | 05/06/2008 |
| 7292177 | Counter circuit, AD conversion method, AD converter, semiconductor device for detecting distribution of physical quantities, and electronic apparatus An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-in... | 11/06/2007 |
| 7253666 | Clock frequency divider circuit and method of dividing clock frequency A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic cont... | 08/07/2007 |
| 7215163 | Method and device for frequency division and demultiplexing A device and method is described for the frequency division of an input clock signal, in which from the input clock signal at least two output clock signals are generated, with an output pulse frequency equal to an input pulse frequency divided by a given factor, wh... | 05/08/2007 |
| 7207324 | Air-intake duct system for a combustion engine The invention relates to an air-intake duct system (1) in which a throttle valve (40), an exhaust gas recirculating valve (29), a bypass valve (19), an exhaust gas cooler (11), against which exhaust gas flows via bypass valve (1... | 04/24/2007 |
| 7203859 | Variable clock configuration for switched op-amp circuits A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the individual operational amplifiers. The length of the off-phase can be adapted ... | 04/10/2007 |
| 7196559 | Multi-modulus divider for high speed applications A multi-modulus divider for high speed applications is provided and may comprise a multistage divider generating a divided signal from an output portion of a divider module for a current stage. The divided signal may be fed back to an input portion of the divider mo... | 03/27/2007 |
| 7109762 | Frequency-dividing circuit arrangement and phase locked loop employing such circuit arrangement A frequency-dividing circuit arrangement is disclosed that includes a divider chain having a plurality of frequency divider stages. The frequency dividers can be changed over between the division ratios 2 and 3. At least that frequency divider that is arranged on th... | 09/19/2006 |
| 7106110 | Clock dithering system and method during frequency scaling A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for... | 09/12/2006 |
| 7092479 | Ripple counter circuits in integrated circuit devices having fast terminal count capability and methods of operating the same Ripple counter circuits in integrated circuit devices can have fast terminal count capability. A terminal count circuit can be configured to mask selected unstable counter bits generated by a ripple counter circuit using an indication that a terminal state of the ri... | 08/15/2006 |
| 7042257 | Frequency divider with reduced jitter and transmitter based thereon An apparatus for generating an output signal whose frequency is lower than the frequency of an input signal is disclosed. The apparatus includes a chain of frequency dividing cells where each cell has a definable division ratio. Furthermore, the frequency dividing c... | 05/09/2006 |
| 6995589 | Frequency divider for RF transceiver A frequency divider for dividing a frequency of a clock signal by an odd divisor includes a flip-flop chain for latching signals having a number of flip-flops equal to the divisor. The frequency divider also has an XOR gate having two input nodes and an output node,... | 02/07/2006 |
| 6952121 | Prescaling for dividing fast pulsed signal Circuits, devices and methods are provided for dividing a fast pulse signal by an integer M. A dual modulus prescaler receives input pulses, counts them, and generates one prescaled pulse for every Qth input pulse. Q is a division modulus, and has a different value ... | 10/04/2005 |
| 6943713 | Process and device for the sequential addressing of the inputs of a multiplexer of a data acquisition circuit The systematic, and possibly repeated, acquisition of several distinct quantities for exploitation by a user system by utilizing a multiplexer with staged architecture without all inputs hard-wired. Each multiplexer stage is addressed by an elementary counter chaine... | 09/13/2005 |
| 6928387 | Circuit and method for distributing events in an event stream A circuit and method for distributing events in an event stream. A circuit for distributing events in a signal into a plurality of channels of circuitry capable of timestamping events is described. The circuit includes a first plurality of flip-flops arranged in a c... | 08/09/2005 |
| 6597211 | Clock divider circuit producing 0° and 90° outputs with a 50% duty cycle A clock divider circuit producing 0° and 90° outputs with a 50% duty cycle is provided. In one embodiment, the clock divider circuit may include a pair of cross-coupled circuits. The clock divider circuit may produce a first output clock signal and a se... | 07/22/2003 |
| 6504407 | Programmable high speed frequency divider A programmable high speed frequency divider, in which flip-flops for forming a frequency divider which is capable of being programmed with a programmable dividing ratio is simplified increase the speed of the frequency divider. By simplifying the least si... | 01/07/2003 |
| 6026140 | Low power programmable ripple counter A ripple counter becomes programmable by use of intervening circuitry selectively inhibiting state transitions according to an initial programming step. The illustrated embodiment of a programmable ripple counter includes a forward chain of count register... | 02/15/2000 |
| 5978437 | Binary counter system using bit-wise matches with maximum count A counting system with a dynamic maximum count includes a counter, match logic, and a maximum count controller. The counter has a present count register, a clock (or event indicator) event input, and a reset input. The maximum count controller can be prog... | 11/02/1999 |
| 5907591 | High speed programmable counter A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proc... | 05/25/1999 |
| 5877657 | PLL clock generator having trimmable frequency dividers A reference clock signal oscillator generates a reference clock signal. A first programmable counter performs frequency dividing on the reference clock signal and outputs a reference signal resulting-from the frequency dividing. A voltage controlled oscil... | 03/02/1999 |
| 5666390 | High speed programmable counter A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proc... | 09/09/1997 |
| 5590163 | Frequency divider circuit, frequency synthesizer comprising such a divider and radio telephone comprising such a synthesizer Frequency divider circuit, frequency synthesizer comprising such a divider and radio telephone comprising such a synthesizer. A frequency divider circuit according to the invention includes a succession of N divide-by-two or divide-by-three dividing cells... | 12/31/1996 |
| 5557649 | Circuit configuration for dividing a clock signal A circuit configuration being made by differential technology for dividing a clock signal with switchable divider ratios of 4/5 by emitter coupled logic, includes first, second and third series-connected flip-flops each having an output, a data input and ... | 09/17/1996 |
| 5383230 | Reload-timer/counter circuit A reload-timer/counter circuit provides a reload-timer function and a counter function commonly and selectively. The circuit is comprised of first, second, third, and fourth registers. The third and fourth registers act as a control status register and a ... | 01/17/1995 |
| 5253279 | Semiconductor integrated circuit having a built-in programmable divider A semiconductor integrated circuit includes an input terminal provided for each of input terminals. The input circuit outputs either one of "HIGH" or "LOW" as a frequency dividing ratio setting signal when the corresponding input terminal is "HIGH" or "LO... | 10/12/1993 |
| 5124597 | Timer circuit including an analog ramp generator and a CMOS counter A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp ... | 06/23/1992 |
| 5111487 | Electronic timer apparatus Modulo timer apparatus including a chain of modulo counter stages is controllable by write signals generated by a central controller. The central controller is operative to generate a write signal corresponding to a selected counter stage, and a digital c... | 05/05/1992 |
| 5065415 | Programmable frequency divider A programmable frequency divider for dividing the frequency of a supplied high-frequency signal directly into a lower frequency includes a plurality of 2-scale-factor prescalers or programmable frequency divider units each capable of being switched betwee... | 11/12/1991 |
| 5029191 | Binary counter with resolution doubling A binary counter (60) provides for resolution doubling by producing a wavetrain (Q0) which represents the zero-order bit of the counter and has the same frequency as the clock input (REFCLOCK).... | 07/02/1991 |
| 5020082 | Asynchronous counter An asynchronous nonlogical counting device includes at least a first counter and a second counter connected in cascade. The first counter has a frequency dividing ratio of 2n where n is a natural number. A control unit produces a control signal... | 05/28/1991 |
| 4989224 | Coincidence circuit A coincidence circuit for detecting when n-bit binary input data coincides with the current value of an n-bit counter. A plurality of "1" detecting circuits determine, when a corresponding input bit is one, whether a corresponding counter bit is also one.... | 01/29/1991 |
| 4975931 | High speed programmable divider A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the... | 12/04/1990 |
| 4951303 | High speed digital programmable frequency divider A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing a periodic input w... | 08/21/1990 |
| 4935944 | Frequency divider circuit with integer and non-integer divisors A frequency divider circuit for dividing an input signal with a predetermined integer or non-integer divisor. The frequency divider circuit comprises a polynomial counter, decode logic, and a clock edge selector. The polynomial counter, responsive to a cl... | 06/19/1990 |
| 4891825 | Fully synchronized programmable counter with a near 50% duty cycle output signal A method and arrangement for a fully synchronized, programmable frequency divider is disclosed that exhibits a near 50% duty cycle output signal independent of the divisor, whether even or odd, and that is suitable for use in a phase-locked loop (PLL) fre... | 01/02/1990 |
| 4879733 | Timer architecture for multi-task computers and for serial data decoding A timer which can be used to provide interrupt signals at predetermined but variable periods for multi-tasking microcomputers or serial data acquisition in pagers comprises a plurality of modulo counters. Each modulo counter has selectable clock inputs an... | 11/07/1989 |
| 4815114 | Elementary binary counter, synchronous binary counter and frequency divider in which said elementary counter is employed A stable binary counter as applicable to synchronous counters, to frequency dividers and more particularly to microwave integrated circuits is constituted by a plurality of elementary counters mounted in cascade. Each elementary counter is formed by a hal... | 03/21/1989 |
| 4754163 | Pulse generator with adjustable pulse frequency, pulse width and pulse delay A pulse generator with adjustable pulse frequency, pulse width and pulse delay contains a start-stop oscillator (1) whose oscillator pulses are counted by a counter (2) in adjustable counting cycles. After each counting cycle, the oscillator (1) is shut d... | 06/28/1988 |
| 4745629 | Duty cycle timer An improved duty cycle timer provides a duty cycle control signal having alternate "on" and "off" intervals of different logic states. The timer utilizes integrated circuitry having first and second independent clock sources respectively driving first and... | 05/17/1988 |
