Class 375/376 - Phase locked loop

Subclass of Class 375 - Pulse or digital communications
Definition: Subject matter having a closed-loop electronic servomechanism
No. of patents: 3084
Last issue date: 02/07/2012

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Number	Title	Issue Date
8111800	Frequency ratio detection A system and method are provided for determining a frequency ratio in a phase-locked loop (PLL) circuit feedback path. The method accepts a reference signal having a predetermined first frequency and a PLL output signal having a non-predetermined second frequency. T...	02/07/2012
8111799	Method, system and apparatus for reducing power consumption at low to midrange resolution settings A method for reducing power consumption in an information handling system (IHS) where the method includes receiving main data through a main link, wherein the main link provides at least one data lane. The IHS also receives a reference clock corresponding to the mai...	02/07/2012
8107582	Methods and apparatus for digital clock recovery A method and apparatus for clock recovery in synchronous digital systems. The apparatus includes a phase frequency detector, a loop filter, a compressor, and a clock generator. The phase frequency detector generates a phase error signal based on a difference between...	01/31/2012
8107581	Method for frequency compensation in timing recovery A method of digitally controlling a timing recovery loop to control jitter and reduce word-length in a recovered clock is provided. A timing error detector provides an output identifying the error sign. First and second randomizing digital attenuators provide first ...	01/31/2012
8098788	System and method for automatic leakage control circuit for clock/data recovery and charge-pump phase locked loops An apparatus that includes a module for controlling the frequency of a voltage controlled oscillator (VCO) as part of a phase locked loop (PLL), or clock and data recovery (CDR) when an input reference signal to the PLL or serial data to the CDR has ceased from bein...	01/17/2012
8098787	Method and apparatus for precision quantization of temporal spacing between two events One or two Serializer/Deserializer (SerDes) modules are used to measure the time between two pulses with high resolution. A PLL inside a SerDes block is locked to a reference clock and an input signal is passed through a storage element to create a serial data strea...	01/17/2012
8094770	Dynamic phase tracking using edge detection that employs an edge counter A phase-locked loop includes a sample selector configured to select a set of samples from an oversampled portion of a data signal, a dynamic phase decision control circuit configured to indicate whether a predetermined number of edges is present in the set of sample...	01/10/2012
8094769	Phase-locked loop system with a phase-error spreading circuit A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit...	01/10/2012
8090070	Synchronizing device for USB real-time audio data transmission The present invention discloses a synchronizing device for real-time USB audio data transmission, comprising: a first adder unit, a start-of-frame countdown unit, a phase-locked loop circuit, a frequency divider, a second adder unit, a third adder unit, a fourth add...	01/03/2012
8090068	System and method of calibrating power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL) A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating th...	01/03/2012
8090069	Apparatus for generating clock signal with jitter and test apparatus including the same The present invention relates to an apparatus for generating a clock signal with jitter and a test apparatus including the same. The apparatus for generating a clock signal with jitter in accordance with the present invention includes a voltage-controlled crystal os...	01/03/2012
8085893	Low jitter clock recovery circuit A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjus...	12/27/2011
8077822	System and method of controlling power consumption in a digital phase locked loop (DPLL) An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering ...	12/13/2011
8064562	Digital frequency locked delay line A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a ...	11/22/2011
8059777	Method and apparatus for generating phase shifted local oscillator signals for a feedback loop on a transmitter A transmitter is provided with a local oscillator (LO) processing unit to maintain stability in the transmitter's feedback loop. The LO processing unit includes at least one delay locked loop (DLL) and a programmable divider to generate phase shifted LO signals for ...	11/15/2011
8059778	Automatic clock frequency acquisition A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecti...	11/15/2011
8054931	Systems and methods for improved timing recovery Various embodiments of the present invention provide systems and methods for improved timing recovery. As one example, some embodiments of the present invention provide timing recovery circuits that include an error signal and a digital phase lock loop circuit. The ...	11/08/2011
8054930	Clock recovery circuit A circuit is provided for clock recovery. The circuit includes a reference extraction unit for extracting from a datastream time references defining a reference time base, and a digital Phase Locked Loop including a first programmable counter in the guise of a digit...	11/08/2011
8050376	All digital phase-locked loop with widely locked frequency An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a ...	11/01/2011
8045670	Interpolative all-digital phase locked loop An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF ...	10/25/2011
8045669	Digital phase-locked loop operating based on fractional input and output phases In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference bet...	10/25/2011
8040995	Jitter detection circuit and jitter detection method A jitter detection circuit includes an oscillation circuit, a measurement period setting circuit for outputting a measurement period signal based on a measurement period specifying signal, the measurement period setting circuit receiving the output clock from a PLL ...	10/18/2011
8040996	Method and system for RF signal generation utilizing a synchronous multi-modulus divider Aspects of a method and system for RF signal generation utilizing a synchronous multi-modulus divider are provided. In this regard, a feedback signal of a PLL may be generated by clocking a counter with an RF signal output by the PLL and toggling the feedback signal...	10/18/2011
8040994	Phase coefficient generation for PLL A method and apparatus is provided for synchronizing a clock signal by generating time varying PLL phase coefficients which approximate optimal PLL phase coefficients. An acquisition mode phase coefficient is determined by adding an error signal (A) to the sample co...	10/18/2011
8036334	Delay lock loop phase glitch error filter A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop...	10/11/2011
8027423	Synchronizing apparatus, synchronizing method, synchronizing program and data reproduction apparatus A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for ...	09/27/2011
8023608	Communication system using multi-phase clock signals A communication system using multi-phase clock signals. The communication system includes a transmitter and a receiver. The transmitter outputs first data and a clock signal based on first multi-phase clock signals, and performs a coarse lock operation on the clock ...	09/20/2011
8014485	Techniques for integrated circuit clock management using multiple clock generators A clock generator system (400) includes a phase locked loop (PLL) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first...	09/06/2011
8014486	Generating a frequency switching local oscillator signal Methods and systems of generating a frequency switching local oscillator signal are disclosed. One method includes generating a reference clock signal, and clocking a counter with the reference clock signal. The counter controls selection of a one of a plurality of ...	09/06/2011
8009786	Method for agile region and band conscious frequency planning for wireless transceivers A technique for agile region and band conscious frequency planning for wireless transceivers in which a comparison frequency is selected for generating a local oscillator signal. The comparison frequency (Fcomp) is selected for a frequency band of a parti...	08/30/2011
8000430	Wide frequency range delay locked loop A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and...	08/16/2011
7995697	Polar modulation / one-point frequency modulation with flexible reference frequency Apparatuses and methods for operating a modulation system using a flexible reference frequency signal are disclosed. A modulation system uses a phase-locked loop (PLL). An internal reference signal source is configured to provide an internal reference signal having ...	08/09/2011
7995698	Method for binary clock and data recovery for fast acquisition and small tracking error A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to gen...	08/09/2011
7995699	DLL circuit with wide-frequency locking range and error-locking-avoiding function A delay-locked loop (DLL) circuit. In the evaluation period, the DLL circuit adjusts needed delay period of time for a reference clock signal by adjusting the amount of the used delay units which each of has fixed delay period of time digitally and controlling the d...	08/09/2011
7991103	Systems and methods for data recovery in an input circuit receiving digital data at a high rate Embodiments include systems and methods for recovery of data from an incoming digital data stream. Embodiments comprise a fine tracking loop to track the data when the phase between the incoming data and the receiver clock varies relatively slowly. Embodiments compr...	08/02/2011
7991102	Signal generating apparatus and method thereof A signal generating apparatus includes: a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a ...	08/02/2011
7983375	Variable delay oscillator buffer A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signa...	07/19/2011
7974375	Linear phase detector and clock/data recovery circuit thereof A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions ...	07/05/2011
7974376	High precision continuous time gmC BPF tuning High precision continuous time gmC BPF (Band Pass Filter) tuning. A novel approach is presented by which a continuous time signal serves as a BPF control voltage for tuning of a BPF within a communication device (e.g., transceiver or receiver). A PLL (Pha...	07/05/2011
7974374	Multi-mode VCO for direct FM systems Systems for multi-mode phase modulation are disclosed. Systems provide for direct modulation of a multi-mode voltage controlled oscillator (VCO). A fractional-N counter may be used in a phase-locked loop (PLL) to synthesize a radio frequency carrier signal. The mult...	07/05/2011

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Class 375/376 - Phase locked loop