"I hate what they've done to my child...I would never let my own children watch it. "
Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Number | Title | Issue Date |
| 8149980 | System and method for implementing a phase detector to support a data transmission procedure A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a volta... | 04/03/2012 |
| 8130891 | Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive ... | 03/06/2012 |
| 8111798 | Phase synchronization circuit and receiver having the same A phase synchronization circuit includes a controlled oscillator configured to generate a first oscillation signal and a second oscillation signal that have a common frequency but different phase controlled by a combination of a first control signal and a second con... | 02/07/2012 |
| 8036333 | Clock and data recovery circuit and method of recovering clocks and data A clock and data recovery circuit that does not use a reference clock and a method of recovering cocks and data, in which the clock and data recovery circuit includes a clock generation unit, a mirror delay unit, a preamble phase detection unit, and a sampling unit.... | 10/11/2011 |
| 8023607 | Frequency synchronization method and apparatus A frequency synchronization method comprise a first step of detecting a frequency error which occurs when a high-frequency receiving signal is converted into a digital signal of a base-band, performing rounding or discarding processing and generating a local oscilla... | 09/20/2011 |
| 8019037 | Phase difference detection device and rotation position detection device A phase difference detection device able to detect a phase with a high precision is provided. A phase difference detection device 4 detecting a phase difference θ between an excitation signal Ss and a second detection signal Sd in accordance with a rotation ... | 09/13/2011 |
| 7961832 | All-digital symbol clock recovery loop for synchronous coherent receiver systems A symbol clock (16) associated with a symbol stream (5) in a synchronized communication receiver can be recovered by adjusting the phase of a symbol clock signal (12). The phase adjustment is accomplished by applying a digitally controlled delay... | 06/14/2011 |
| 7949081 | Phase detecting circuit and clock generating apparatus including the same A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a dat... | 05/24/2011 |
| 7894564 | Phase modulation method for spread spectrum clock generator Spread spectrum clock generation (SSCG) using phase modulation. A first clock signal having a first frequency spectrum may be modulated using phase modulation to produce a second clock signal. The phase modulation may include providing a phase modulation profile cor... | 02/22/2011 |
| 7894563 | Clock recovery circuit and a method of generating a recovered clock signal The present invention relates to a clock recovery circuit for generation of a recovered clock signal from a received data stream using a weighted combination of phase component signals. The clock recovery circuit comprises: a detector to detect the phase of a receiv... | 02/22/2011 |
| 7885368 | Analog phase controller Disclosed are embodiments of a phase control circuit with an analog phase controller that is able to effectively generate control signals for all four quadrants of phase control operation. ... | 02/08/2011 |
| 7873130 | Frequency comparator utilizing enveloping-event detection via symbolic dynamics of fixed or modulated waveforms Systems, algorithms, circuits, and methods for pattern detection of signature events in signal dynamics defined by instantaneous states of applied square-wave signals. Selected patterns may be recognized individually or in equivalence classes, and detection may be i... | 01/18/2011 |
| 7864911 | System and method for implementing a phase detector to support a data transmission procedure A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a volta... | 01/04/2011 |
| 7864912 | Circuits, architectures, a system and methods for improved clock data recovery Circuits, architectures, a system and methods for clock data recovery. The circuit generally includes a clock phase adjustment circuit, receiving clock phase information and providing a clock phase adjustment signal, a clock frequency adjustment circuit, receiving c... | 01/04/2011 |
| 7831006 | Circuit to reduce transient current swings during mode transitions of high frequency/high power chips An apparatus is provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimi... | 11/09/2010 |
| 7826582 | Numerically controlled oscillator (NCO) output clock phase smoothing A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input c... | 11/02/2010 |
| 7817766 | Apparatus and method for avoiding steady-state oscillations in the generation of clock signals A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift ... | 10/19/2010 |
| 7804926 | PLL using unbalanced quadricorrelator A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits ( | 09/28/2010 |
| 7778375 | Clock generator and data recovery circuit using the same A clock generator and a data recovery circuit. The clock generator includes a voltage control oscillator (VCO) for generating a sampling clock and multi-phase clocks, a multiplexer for receiving the multi-phase clocks and selecting one of the multi-phase clocks to g... | 08/17/2010 |
| 7778376 | Static phase adjust using LC tanks with offset center frequencies A phase detector includes a first clock driver comprising a first LC tank. The first clock driver provides a strobe to a plurality of flip-flops associated with sampled data being received by the phase detector. The second clock driver includes a second LC tank. The... | 08/17/2010 |
| 7769122 | Timing recovery circuit A timing recovery circuit capable of enhancing the reliability of timing recovery in a receiver apparatus in a communication system that employs the scheme of modulating the amplitude of a carrier wave. In the receiver apparatus which receives a transmitted signal c... | 08/03/2010 |
| 7756236 | Phase detector A phase detector is described, comprising a pair of output-latched half-transparent (OLHT) module each receiving two input terminals with an inverse connection relationship with respect to two input signals as compared to each other, wherein each OLHT module of the ... | 07/13/2010 |
| 7751521 | Clock and data recovery apparatus A clock and data recovery apparatus reduces current consumption and enables easy integration. The inventive apparatus includes a first loop including a frequency/phase detection unit, a first charge pump unit, a multiplexing unit, a filtering unit, and a voltage con... | 07/06/2010 |
| 7738618 | Multiband PLL arrangement and a method of controlling such arrangement The present invention relates to a multiband PLL arrangement comprising a single loop PLL with a phase/frequency detecting means (1), a loop filter means (2) and a Voltage Controlled Oscillator (VCO) (3), to which PLL a reference voltage signal ... | 06/15/2010 |
| 7734000 | Clock and data recovery circuits A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a significant transition of an input signal. Each oscillator receives the detec... | 06/08/2010 |
| 7715514 | Clock and data recovery circuit A clock and data recovery circuit that tracks the frequency and phase fluctuation of serial data includes a feedback controller for monitoring tracking speed of an extraction clock with respect to the frequency and phase fluctuation of the serial data and applying f... | 05/11/2010 |
| 7672417 | Clock and data recovery A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes; a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input ... | 03/02/2010 |
| 7668278 | Phase-locked loop An oscillator (30) supplies a high frequency signal (S) to a frequency divider (31). A phase comparator (32) produces a signal measuring phase difference between the divided frequency signal (QA) and a reference signal. A low-pass filter (34 | 02/23/2010 |
| 7664215 | Signal alignment based on data signal Alignment of a receiver clock signal with a transmitter clock signal based upon a received data signal is disclosed. Some embodiments generate, based upon of phase bits and valid phase bits, a phase signal having a voltage level selected from at least three voltage ... | 02/16/2010 |
| 7656986 | Low jitter phase rotator A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having diffe... | 02/02/2010 |
| 7602876 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 10/13/2009 |
| 7583773 | Frequency synthesizing device with automatic calibration A frequency synthesizer with automatic calibration includes a voltage-controlled oscillator, which has several working bands for receiving a coarse-tuned signal and a fine-tuned signal and generating an output signal in the working band of the coarse-tuned signals; ... | 09/01/2009 |
| 7555090 | Communication channel detector and channel detection method A communications channel detector which determines the availability of a desired type of communications channel in a communication system having at least one communications channel, the communications channels including data streams comprising a number of data symbo... | 06/30/2009 |
| 7519139 | Signal monitoring systems and methods Systems and methods are disclosed herein to provide signal monitoring techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a phase detector circuit that receives an input signal and samples the input sign... | 04/14/2009 |
| 7466786 | Rational number frequency multiplier circuit and method for generated rational number frequency A rational number frequency multiplier circuit and a method for generating rational number multiple frequency are disclosed. The circuit receives a plurality of input signals having the same frequency and different phase, and outputs at least one multiple frequency ... | 12/16/2008 |
| 7466785 | PLL with balanced quadricorrelator A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, ... | 12/16/2008 |
| 7447290 | Apparatus of phase-frequency detector An apparatus of phase-frequency detector for adjusting wobble clock signal and wobble signal in the same phase, comprising: a first logic gate, receiving a first protection signal and a second protection signal and outputting a third protection signal according to a... | 11/04/2008 |
| 7443251 | Digital phase and frequency detector Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a p... | 10/28/2008 |
| 7436882 | Decision feedback equalizer and clock and data recovery circuit for high speed applications A method for communicating data includes equalizing received data to reduce channel related distortion in the received data. A clock having frequency and/or phase fixed relative to the equalized data is extracted from the equalized data. The extracted clock is used ... | 10/14/2008 |
| 7436919 | Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles o... | 10/14/2008 |