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"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 8175208 | Method of reducing d.c. offset A method of reducing d.c. offset comprises comparing the a first variable signal with a second variable signal, producing a control signal in dependence upon the comparison, providing the control signal to a charge pump for generation of a feedback signal, and varyi... | 05/08/2012 |
| 8135104 | Serial transceiver and communication method used by the serial transceiver A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver ... | 03/13/2012 |
| 8107580 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 01/31/2012 |
| 8090067 | Circuits and methods for clock and data recovery A clock-data recovery circuit includes a phase rotator, a phase detector and a charge pump. The phase rotator receives first and second reference clocks and differential control signals. The phase rotator generates a modified clock signal responsive to the first and... | 01/03/2012 |
| 8073093 | Phase synchronous device and method for generating phase synchronous signal Disclosed are a phase synchronous device for improving jitter of an output signal and a method for generating a phase synchronous signal. The phase synchronous device includes a phase detector detecting a phase difference between first and second signals to output a... | 12/06/2011 |
| 7957500 | Fast phase-frequency detector arrangement A detector arrangement for detecting a frequency error between an input signal (DATA) and a reference signal. The detector arrangement comprising first latch circuitry (L1, L2) for sampling a quadrature component (CKQ) of the reference signal based on ... | 06/07/2011 |
| 7889826 | Process, voltage, temperature independent switched delay compensation scheme A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay co... | 02/15/2011 |
| 7876871 | Linear phase frequency detector and charge pump for phase-locked loop Techniques for achieving linear operation for a phase frequency detector and a charge pump in a phase-locked loop (PLL) are described. The phase frequency detector receives a reference signal and a clock signal, generates first and second signals based on the refere... | 01/25/2011 |
| 7864910 | Phase locked loop A PLL is provided with an optimum operating point in order to have appropriately a frequency margin and a locking time. There is provided a phase looked loop which includes: a frequency divider for dividing an output signal by a dividing integer corresponding to an ... | 01/04/2011 |
| 7720188 | Fast phase-frequency detector arrangement The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises a first latch circuit for sampling a quadrature component of a reference signal... | 05/18/2010 |
| 7693247 | Phase locked loop having reduced inherent noise A phase locked loop having reduced inherent noise is provided. The phase locked loop comprises a controlled oscillator for outputting a periodic output signal as a result of a control signal; a feedback unit for providing at least two periodic feedback signals havin... | 04/06/2010 |
| 7580497 | Clock data recovery loop with separate proportional path A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO))... | 08/25/2009 |
| 7505542 | Low jitter digital frequency synthesizer with frequency modulation capabilities A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a fi... | 03/17/2009 |
| 7439783 | Phase-locked loop systems and methods Improved common mode feedback techniques are provided for charge pumps, phase-locked loops (PLLs), and other circuits. For example, in accordance with an embodiment of the present invention, a circuit includes a loop filter having first and second loop filter nodes.... | 10/21/2008 |
| 7436920 | Burst mode receiver based on charge pump PLL with idle-time loop stabilizer An improved burst mode receiver includes a digital phase detector, receiving an incoming signal. The receiver also includes a charge pump, receiving pulse signals from the digital phase detector to compare the incoming clock phase to the local generated clock phase ... | 10/14/2008 |
| 7436919 | Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles o... | 10/14/2008 |
| 7433442 | Linear half-rate clock and data recovery (CDR) circuit A linear, half-rate clock and data recovery (CDR) circuit for recovering clock information embedded in a received data signal. The half-rate CDR circuit comprises a phase detector that may receive the data signal and generate a phase error signal representative of t... | 10/07/2008 |
| 7428169 | Nonvolatile semiconductor memory device and voltage generating circuit for the same A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage ge... | 09/23/2008 |
| 7424078 | Synchronous compensator adaptively defining an enable range for synchronous compensation In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable signal from a synchronous compensator circuit, thereby excluding the ... | 09/09/2008 |
| 7424081 | Semiconductor integrated circuit device An error rate of a bit synchronous circuit is decreased to a large extent by preventing following excessively the jitters included in input data. A phase detect circuit of a bit synchronous circuit includes a majority decision circuit. The majority decision circuit ... | 09/09/2008 |
| 7421052 | Oscillator frequency selection According to some embodiments, a frequency adjuster adjusts a frequency of an oscillator. For example, the frequency adjuster might include a plurality of capacitors that are selectable using a digital control signal, and selection logic may adjust the digital contr... | 09/02/2008 |
| 7418071 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 08/26/2008 |
| 7408391 | Charge pump for PLL/DLL A charge pump for use in a Phase Locked Loop/Delay Locked Loop. The charge pump includes a pull-up circuit a pull-down circuit and a reference current source. The reference current source includes a number of select transistors and a number of mirror master transist... | 08/05/2008 |
| 7409027 | System and method for recovering a clock using a reduced rate linear phase detector and voltage controlled oscillator An improved clock recovery system, phase-locked loop, and phase detector are provided as well as a method for generating charge pump signals. The clock recovery system includes a phase-locked loop. The phase-locked loop includes a phase detector and a voltage-contro... | 08/05/2008 |
| 7400690 | Adaptive phase controller, method of controlling a phase and transmitter employing the same The present invention is directed to an adaptive phase controller employing a threshold level and a method of controlling a phase. In one embodiment, the adaptive phase controller includes a comparator configured to receive a comparison signal representing a phase a... | 07/15/2008 |
| 7397882 | Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase compar... | 07/08/2008 |
| 7386085 | Method and apparatus for high speed signal recovery A closed-loop circuitry includes, in part, a loop filter and a current source/sink coupled to the loop filter to adjust the phase/frequency of the signal generated by the closed-loop circuitry. Because the voltage generated by the loop filter has a relatively low fr... | 06/10/2008 |
| 7386065 | Voltage controlled oscillator (VCO) suitable for use in frequency shift keying (FSK) system A voltage controlled oscillator (VCO), suitable for use in a frequency shift keying (FSK) system. The VCO device comprises a switching varactor unit, having a first terminal and a second terminal, wherein the switching varactor unit produces a capacitance, according... | 06/10/2008 |
| 7382849 | Charge pump circuit Charge pump circuit. A charge pump circuit is provided for use in a phase-lock loop circuit. The charge pump circuit comprises a charge pump core circuit that outputs a control voltage. The charge pump circuit also comprises a replica circuit that is coupled to the ... | 06/03/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7365581 | Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pum... | 04/29/2008 |
| 7356077 | Method and apparatus for testing network integrity Apparatuses and methods for testing the integrity of high speed optical fiber transmission networks are presented. Data from an optical network, for example, NRZ formatted data at forty gigabits per second and higher may be reliably recovered using embodiments of th... | 04/08/2008 |
| 7349513 | Process, voltage, temperature independent switched delay compensation scheme A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay co... | 03/25/2008 |
| 7336110 | Differential amplitude controlled sawtooth generator A dual differential sawtooth signal generator includes a first sawtooth voltage generator that has a first capacitor and a second capacitor that are alternately charged with a feedback control source current from a low voltage reference voltage level. A second sawto... | 02/26/2008 |
| 7332947 | Method and apparatus for distorting duty cycle of a clock An apparatus for controllably distorting the duty cycle of a clock signal is disclosed. Methods and systems using embodiments of the invention are also described. ... | 02/19/2008 |
| 7334148 | Optimization of integrated circuit device I/O bus timing The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting... | 02/19/2008 |
| 7330060 | Method and apparatus for sigma-delta delay control in a delay-locked-loop Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and... | 02/12/2008 |
| 7323402 | Trench Schottky barrier diode with differential oxide thickness A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination... | 01/29/2008 |
| 7324421 | Method and apparatus for data bit align An invention is provided for data bit align. The invention includes a multiplexer that receives a data sample word as data input and also receives a clock sample word as select input. The multiplexer selects a data bit from the data sample word based on the clock sa... | 01/29/2008 |
| 7323915 | Delay locked loop with selectable delay A DLL includes a control module coupled with a phase detect signal. The phase detect signal is used by a control module to generate feedback and output select signals. The feedback and output select signals are each coupled to a multiplexer. Each multiplexer is coup... | 01/29/2008 |
