Class 375/372 - Elastic buffer

Subclass of Class 375 - Pulse or digital communications
Definition: Subject matter wherein a first in-first out (FIFO) storage
No. of patents: 619
Last issue date: 01/03/2012

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
8090066	Method and circuit for obtaining asynchronous demapping clock A method and a circuit for obtaining asynchronous demapping clock. The method includes: obtaining a smoothed clock with even gaps in accordance with data to be demapped and a corresponding clock signal; performing phase locking in accordance with a signal reflecting...	01/03/2012
8050374	Semiconductor memory device capable of controlling tAC timing and method for operating the same A semiconductor memory device is capable of controlling a tAC with a timing margin in an output data process. The semiconductor memory device includes a delay locked loop circuit, a tAC control unit, a reference signal generating unit, and a data output block. The d...	11/01/2011
RE42829	Method and apparatus for compensating reproduced audio signals of an optical disc An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audi...	10/11/2011
RE42792	Method and apparatus for compensating reproduced audio signals of an optical disc An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audi...	10/04/2011
RE42791	Method and apparatus for compensating reproduced audio signals of an optical disc An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audi...	10/04/2011
8019035	Noise shaped interpolator and decimator apparatus and method Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to...	09/13/2011
7995696	System and method for deskewing data transmitted through data lanes A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a data buffer for each data stream that stores a minima...	08/09/2011
7986759	Data output method, data output apparatus and communication system A data output apparatus accumulates received sound data in an accumulating unit (jitter buffer), and reproduces sound based on the accumulated sound data. Then, for a predetermined period of time from the time point at which reception of data starts, the data output...	07/26/2011
7978803	Semiconductor device An improved reception port for receiving packet data based on the IEEE 1394 standard. The reception port includes a synchronization FIFO memory for receiving reception data in accordance with a reception clock signal and synchronizing the reception data with an inte...	07/12/2011
7817765	Digital transmission apparatus and methods PCR jitter is improved when writing an input stream TS having a packet with a PCR in a memory 10 and reading it at a high speed. An oscillator 44 oscillates a local clock signal having a frequency of a reference clock for the input TS and a counter ...	10/19/2010
7792234	Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or mo...	09/07/2010
7778373	Sampling rate mismatch solution Methods and apparatuses for compensating for differences in communication system transmit and receive clock signal frequencies include buffer timing modification and sample addition. In buffer timing modification, a buffer clock signal is interrupted as needed to sl...	08/17/2010
7778372	Data delivery system and method, and receiver and transmitter Provided is a data delivery system including a transmitter which transmits data stream via a network, and a receiver which receives the data stream and stores it into a reception buffer thereof, and decodes the stored data stream. The network has predetermined there...	08/17/2010
7778374	Dual reference input receiver of semiconductor device and method of receiving input data signal A dual reference input receiver, and a method of receiving, wherein the input receiver includes a first input buffer which is synchronized with and enabled by a clock signal, senses a difference between the input data signal and a first reference voltage, and amplif...	08/17/2010
7729466	NICAM system and symbol rate conversion method thereof A NICAM system includes a NICAM deframer, a FIFO buffer and a symbol rate conversion (SRC) unit. The NICAM deframer obtains multiple deinterleaved symbols according to a strobe signal and a data signal in each timing and expands the deinterleaved symbols to correspo...	06/01/2010
7715513	Data synchronization apparatus A data synchronization apparatus is provided. The data synchronization apparatus comprises a first-in first-out buffer (FIFO buffer), a control circuit and a phase-locked loop (PLL). The FIFO buffer receives and stores a plurality of data and provides a FIFO adjustm...	05/11/2010
7680233	Adaptive sampling rate converter Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter” and/or “clock drift” effects, which typically arise where one clock ...	03/16/2010
7639768	Method for improving performance in a mobile device In the operation of a mobile device (such as a cellular telephone or a PDA, i.e. Personal Digital Assistant), which mobile device includes a mobile terminal and a memory module, certain operational signals of the mobile device are multiplexed and demultiplexed, resu...	12/29/2009
7620138	Apparatus for receiving parallel data and method thereof A data reception apparatus adjusts a first clock signal and fetches the data signal in a data buffer, using a data signal in accordance with the adjustment clock signal in such a way that a set-up time and a hold time of the data signal are secured for each bit or f...	11/17/2009
7620137	System and method for clock drift correction for broadcast audio/video streaming A clock rate used in rendering broadcast streaming audio/video data is adjusted to converge on a clock rate associated with broadcasting the streaming data. The clock rate is adjusted by monitoring the buffer depth associated with a receive buffer that stores the in...	11/17/2009
7602875	Sampling rate conversion method and apparatus A sampling apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate. A FIFO storing the first data based on a write control signal and outputs the second data read out based on a read control signal i...	10/13/2009
7599459	Receiving apparatus, data transmission system and receiving method A receiving apparatus receives data sequences, each of which includes plural data blocks, from plural transmission lines, respectively. The apparatus includes plural elastic buffers and a deskew circuit. The corresponding data sequence is written into each elastic b...	10/06/2009
7593499	Apparatus and method for low power routing of signals in a low voltage differential signaling system A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response ...	09/22/2009
7583772	System for shifting data bits multiple times per clock cycle A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of dat...	09/01/2009
7570727	Data transmission controller and sampling frequency converter In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been stored earliest in response to a read request signal. A remaining data am...	08/04/2009
7515671	Method for correcting jitter of transmission data Data is transferred from a transmitter to a data buffer of a receiver according to the clock of the transmitter. When the amount of data in the data buffer exceeds an upper limit, the frequency of the reference clock of the receiver is increased to read the data fas...	04/07/2009
7508895	Oversampling apparatus, decoding LSI chip, and oversampling method An oversampling system (oversampling apparatus), a decoding LSI chip, and an oversampling method capable of decreasing the memory capacity of an output buffer used to oversample and output decoded data for digital audio. ...	03/24/2009
7499516	Methods and apparatus for interface buffer management and clock compensation in data transfers A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a first in first out (FIFO) buffer in each serial channel is described. A look ahead circuit is used to detect a clock compensation pa...	03/03/2009
7496167	Storage efficient sliding window sum A delay buffer includes a first shift register receiving input data and having a shift signal input port. The first shift register right shifts the input data responsive to a shift signal on the shift signal input port. The shift signal is determined based on an eff...	02/24/2009
7460629	Method and apparatus for frame-based buffer control in a communication system A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The decoder buffer level limits are specified in terms of a maximum number of encoded frames (or duration). The transmitter can predict the numb...	12/02/2008
7460630	Device and method for synchronous data transmission using reference signal A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data,...	12/02/2008
7457390	Timeshared jitter attenuator in multi-channel mapping applications A timeshared data tributary mapping system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method buffers data from a plurality of tributaries and stores current buffer-fill information at a rate of about one tributary ...	11/25/2008
7450678	Asynchronous signal input apparatus and sampling frequency conversion apparatus In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A reading section reads the accumulated data successively from the FIF...	11/11/2008
7443940	Alignment mode selection mechanism for elastic interface Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO latches on rising clock edges if the data was sent on rising clock ed...	10/28/2008
7440532	Bit slip circuitry for serial data signals Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least...	10/21/2008
7440531	Dynamic recalibration mechanism for elastic interface A method and apparatus for de-skewing and aligning digital data received over an elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points with...	10/21/2008
7436918	Output stage synchronization Systems and methods for transferring data across clock domains in a manner that avoids metastability of the data and is very tolerant of variations in the clock signals of the different clock domains. One embodiment of the invention comprises a mechanism for passing...	10/14/2008
7428288	Asynchronous transport stream receiver of digital broadcasting receiving system employing DVB-ASI mode and method for transmitting asynchronous transport stream thereof An asynchronous transport stream receiver of a digital broadcasting receiving system connected to MPEG-2 (Moving Picture Experts Group-2) equipment, such as a VOD (Video On Demand) server is disclosed. The inventive receiver includes an FIFO section for storing MPEG...	09/23/2008
7428287	Method and device for synchronizing data transmission between two circuits For synchronising the data transmission between a CMOS circuit (1) and a bipolar circuit (2) a DLL (delayed lock loop) is provided which sets a phase deviation between the operating clocks (CLK1, CLK2) of the two circuits (1, 2), a...	09/23/2008
7424059	Data transfer circuit A transmission unit loads transmission data on a first register and outputs it to a transfer line and starts counting the transmission clock signals in a strobe generation counter according to a transmission clock signal. When the counted value reaches a set value, ...	09/09/2008

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 375/372 - Elastic buffer