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| Number | Title | Issue Date |
| 8189727 | Differential transmitter and auto-adjustment method of data strobe thereof A differential transmitter and an auto-adjustment method of data strobe thereof are provided. The differential transmitter includes a phase-detecting unit, a switching unit, a rising edge strobe unit, and a falling edge strobe unit. The phase-detecting unit detects ... | 05/29/2012 |
| 8189726 | Methods and apparatus for operating a digital communications interface Embodiments of the invention relate to integrated circuits comprising inputs for receiving an input signal and a plurality of clock signals having a predetermined phase relationship. The integrated circuit may include a plurality of track-and-hold devices and a plur... | 05/29/2012 |
| 8189728 | Jitter measurement A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two... | 05/29/2012 |
| 8180012 | ISI pattern-weighted early-late phase detector with function-controlled oscillation jitter tracking An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. An I clock and a function-controlled oscillation cycle phase delay Q clock are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stre... | 05/15/2012 |
| 8181130 | Method for jitter reduction by shifting current consumption A method for jitter reduction in a path of an integrated circuit design is presented. The path is first analyzed to identify a combinatorial logic element bounded between a source element and a destination element. The arrival time of the input signal to the combina... | 05/15/2012 |
| 8180011 | Clock and data recovery loop with ISI pattern-weighted early-late phase detection An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated, where the Q clock has a fixed phase delay with respect to the I clock. The I clock frequency is divided by n, creating a reference clock. A seria... | 05/15/2012 |
| 8175207 | ISI pattern-weighted early-late phase detector with jitter correction An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with Q cloc... | 05/08/2012 |
| 8160195 | Phase drift compensation for sampled signals Methods for processing a signal of interest in an electrical power system are provided, as well as systems and computer program products for carrying out the methods. The methods include obtaining a representative window of data points from the signal of interest; o... | 04/17/2012 |
| 8149977 | Recovering data samples An apparatus recovers synchronous data samples from an asynchronously over-sampled stream of data samples derived from an input signal the spectral characteristic of which is subject to variation. The apparatus comprises an FIR filter having an input for receiving t... | 04/03/2012 |
| 8149978 | Clock/data recovery circuit A clock/data recovery circuit includes a data duty correction circuit which outputs corrected data by correcting the duty of input data in accordance with the level of a correction signal, a clock recovery circuit which generates a recovered clock in synchronism wit... | 04/03/2012 |
| 8149979 | Method and apparatus for handling of clock information in serial link ports A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update... | 04/03/2012 |
| 8139700 | Dynamic quadrature clock correction for a phase rotator system A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpola... | 03/20/2012 |
| 8139701 | Phase interpolation-based clock and data recovery for differential quadrature phase shift keying In one embodiment, a method includes receiving N input streams; generating a recovered clock signal based on the input data bits in the N input streams, the recovered clock signal having a clock frequency and a recovered clock phase; generating a clock signal for ea... | 03/20/2012 |
| 8121241 | Method and apparatus for processing radio frequency signals A method and apparatus for processing a radio frequency (RF) signal is provided. The method includes generating a periodic square wave local oscillator (LO) signal of a first phase, a periodic square wave LO signal of a second phase, and a chopping signal. The metho... | 02/21/2012 |
| 8121240 | Statistical measurement of average edge-jitter placement on a clock signal Phase shift is added between a uttering clock signal and a data bit stream clocked by the clock signal. The phase shift is adjusted until half the data bits are captured (counted) over a measurement period. Adding this amount of phase shift between the clock and dat... | 02/21/2012 |
| 8116417 | Deskewing method and apparatus, and data reception apparatus using the deskewing method and apparatus An up/down detection unit samples a received data signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions, wherein the data sampling clock signal, the first edge sampling clock signal, and the sec... | 02/14/2012 |
| 8094768 | Multi-channel timing recovery system The present invention discloses a novel multi-channel timing recovery scheme that utilizes a shared CORDIC to accurately compute the phase for each tone. Then a hardware-based linear combiner module is used to reconstruct the best phase estimate from multiple phase ... | 01/10/2012 |
| 8081728 | Method and apparatus for clock correction in MIMO OFDM A method of phase correction at a wireless device includes: estimating a phase slope for an OFDM symbol in a data portion of a packet based on an elapsed time from the start of the packet; measuring a residual phase slope from tracking pilots for the OFDM symbol in ... | 12/20/2011 |
| 8077821 | Optimized timing recovery device and method using linear predictor In accordance with a method and apparatus of the present invention, a timing recovery device is disclosed to include a timing correction module responsive to a sampled input signal and adapted to generate a time-corrected signal and to further include a linear predi... | 12/13/2011 |
| 8064561 | Determining a time interval based on a first signal, a second signal, and a jitter of the first signal An apparatus including a circuit configured to determine a jitter of a first signal, and to determine a time interval between a feature in a second signal and a feature in the first signal based on the determined jitter. ... | 11/22/2011 |
| 8045667 | Deserializer and data recovery method A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates a... | 10/25/2011 |
| 8045666 | Spread spectrum clock generator Disclosed are embodiments of methods and circuits to generate spread spectrum clocks. ... | 10/25/2011 |
| 8045668 | Frame synchronization apparatus and its control method A frame synchronization apparatus and method for controlling a frame synchronization process. The frame synchronization apparatus includes a correlation-value computation section; an IQ component select section; and a synchronization-signal outputting section. The c... | 10/25/2011 |
| 8036332 | Communication signal symbol timing error detection and recovery Communication signal symbol timing error detection and recovery apparatus and techniques are disclosed. A communication signal that includes symbols is sampled according to receive symbol timing. The samples are band-edge filtered to provide a filtered output signal... | 10/11/2011 |
| 8031823 | System and method for adaptively deskewing parallel data signals relative to a clock A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality... | 10/04/2011 |
| 8019034 | Common state-space multi-channel digital sample timing phase control of multiple read channels for correlated signals Common sample timing control for sample timing of multiple read channels, wherein the signal clocking of the signals received by the multiple read channels are correlated, for example from parallel tracks of magnetic tape that have been written simultaneously. In on... | 09/13/2011 |
| 8014484 | Stream data recording device, stream data editing device, stream data reproducing device, stream data recording method, and stream data reproducing method When recording stream data, index information and time correction information are recorded in correspondence with the stream data. The index information specifies a position of an invalid section in the stream data. The time correction information specifies a time w... | 09/06/2011 |
| 8009785 | Method and system for implementing a PLL using high-voltage switches and regulators A method and apparatus in an integrated circuit radio transceiver are operable to apply a modified control signal to drive logic that includes a plurality of first devices having a first threshold voltage and a first gate oxide thickness that are both greater than a... | 08/30/2011 |
| 8005180 | Data decision apparatus and error measurement apparatus The object of the present invention is to provide a data decision apparatus and an error measurement apparatus which can set the phase of the clock to the optimum state with respect to the data signal without continuously sweeping of the phase, and can keep the stat... | 08/23/2011 |
| 8000429 | Jitter correction method and circuit In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of data 1 clock prior to and a head bit of data 1 clock subsequent to the referenced data is sequentially generated. Each bit of the combinat... | 08/16/2011 |
| 7995695 | Data alignment method for arbitrary input with programmable content deskewing info In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provi... | 08/09/2011 |
| 7983374 | Methods and systems for providing variable clock rates and data rates for a SERDES A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock frequency is shown. According to this method and apparatus, a PMA rate signal ... | 07/19/2011 |
| 7978802 | Method and apparatus for a mesochronous transmission system A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain o... | 07/12/2011 |
| 7965805 | Signal generator with signal tracking Frequency and phase of an output signal is adjusted to track an input signal. A control signal is adjusted to control a frequency of an oscillating signal from which the output signal is derived. In some aspects the frequency of the oscillating signal is adjusted by... | 06/21/2011 |
| 7957499 | Apparatus and method for compensating timing offset in broadband wireless communication system Provided is an apparatus and method for compensating a timing offset in a broadband wireless communication system. A receiving apparatus for the timing offset compensation includes a selector, a first calculator, and a second calculator. The selector groups two or m... | 06/07/2011 |
| 7953199 | Synchronization error tracking device and method thereof Provided is a synchronization error tracking device and method. The method and system estimates and corrects the synchronization error generated by time and frequency offsets during the data transmission interval and uses a module designed for initial synchronizatio... | 05/31/2011 |
| 7945009 | Jitter measurement A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two... | 05/17/2011 |
| 7945010 | Apparatus and method for compensating for phase jump of reference signal in digital phase-locked loop/frequency-locked loop An apparatus and method for compensating for a phase jump of a reference signal in a digital Phase-Locked Loop (PLL)/Frequency-Locked Loop (FLL) are provided. The apparatus includes a phase discriminator for comparing a phase of an external clock signal (i.e., the r... | 05/17/2011 |
| 7940877 | Signal edge detection circuitry and methods Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-... | 05/10/2011 |
| 7936857 | Phase selector for data transmitting device A phase selector is disclosed. The phase selector is utilized for outputting an output clock to a flip-flop according to an input data signal latched by the flip-flop. The phase selector includes: a clock phase adjustor, for adjusting the delay of an input clock to ... | 05/03/2011 |
