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| Number | Title | Issue Date |
| 7929655 | Asynchronous multi-clock system A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of ... | 04/19/2011 |
| 7680231 | Adaptive variable length pulse synchronizer An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchrono... | 03/16/2010 |
| 7376208 | Reception method for packetized information with automatic repeat request A decoding method is carried out in a receiver configured to accept format information relating to sequences of input data, to use format information in the decoding of each input sequence, and to issue an acknowledgement signal in the event that an input sequence i... | 05/20/2008 |
| 7376190 | Asynchronous data transmitting apparatus An asynchronous data transmitting apparatus includes data signal transmission lines; two control transmission lines having a minimum delay and maximum delay respectively; a transmitter; and a receiver. The transmitter includes a data transmitting unit that transmits... | 05/20/2008 |
| 7372826 | Providing advanced communications features Advanced communications features are provided in a mobile communications network having at least one mobile switching center and at least one mobile station subsystem. The mobile switching center and mobile station subsystem each communicate signaling messages accor... | 05/13/2008 |
| 7369636 | Asynchronous communication circuit A counter value of a divider counter 3 that determines a communication speed is compared by a comparator 4 with a value calculated from a difference between fall delay and rise delay, and data is received with a matching signal serving as a data recept... | 05/06/2008 |
| 7340023 | Auto baud system and method and single pin communication interface In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits cou... | 03/04/2008 |
| 7333536 | System and method for auto baud rate detection in asynchronous serial communication A microcontroller with embedded software for automatically detecting a baud rate of an asynchronous serial bit stream during an initial set up phase of a microcontroller. The microcontroller is configured to receive a data set from a transmitter and includes a trans... | 02/19/2008 |
| 7321615 | At-command analyzing method An UART receives asynchronous transmission serial data based on a baud-rate clock from a DTE. An MPU analyzes the data received by the UART. A baud-rate generating portion generates the baud-rate clock to be output to the UART in accordance with instructions from th... | 01/22/2008 |
| 7317775 | Switched deskew on arbitrary data A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first samplin... | 01/08/2008 |
| 7298290 | DSRC controller and a method therefor In a DSRC communications controller equipped with a plurality of reception means for DSRC communications according to the invention, a reception reservation storage section 104 comprises means for detecting a communications frame start signal (unique word ... | 11/20/2007 |
| 7287113 | Method of and apparatus for controlling bidirectional streams of isochronous data flowing between an application and a bus structure An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any number of ... | 10/23/2007 |
| 7231009 | Data synchronization across an asynchronous boundary using, for example, multi-phase clocks Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determi... | 06/12/2007 |
| 7199989 | Digital protection relay with time sync function In a digital protection relay with a time sync function, the sampling timing of which is specified based on a reference timing transmitted from a time signal generator to a time sync unit, with a determination value. The time sync unit includes a reception circuit t... | 04/03/2007 |
| 7199625 | Delay locked loop structure providing first and second locked clock signals A delay locked loop including a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a frequency and to lock onto the clock signal and provide a first locked clock signal over a first frequency range and a second locke... | 04/03/2007 |
| 7194059 | Method and apparatus for skip-free retiming transmission of digital information A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The re... | 03/20/2007 |
| 7180935 | System and method for compensating for delay time fluctuations A method is provided for time control of data transmission from a first module to a further module. An electronic system also is provided having a first module from which data is sent via a connecting line to a further module, which has a reference signal line via w... | 02/20/2007 |
| 7146283 | Calibrating analog-to-digital systems using a precision reference and a pulse-width modulation circuit to reduce local and large signal nonlinearities A calibration unit and technique for calibrating A/D systems (e.g., data acquisition devices) using a pulse-width modulation (PWM) circuit to reduce nonlinearity. The calibration unit may be coupled to an analog-to-digital module (ADM) of the A/D system. The PWM cir... | 12/05/2006 |
| 7123066 | Speed-locked loop to provide speed information based on die operating conditions A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in o... | 10/17/2006 |
| 7119582 | Phase detection in a sync pulse generator A phase detector and phase detection method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock do... | 10/10/2006 |
| 7116739 | Auto baud system and method and single pin communication interface In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits cou... | 10/03/2006 |
| 7110471 | Radio communication control device which can accurately determine the start point of the standby period timer The demodulation unit demodulates a received signal. The detection circuit detects the final data contained in a received data stream supplied from the demodulation unit. When detecting the final data, the detection circuit outputs the final data notification signal... | 09/19/2006 |
| 7099424 | Clock data recovery with selectable phase control A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit, a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase rel... | 08/29/2006 |
| 7095730 | Data transmission with interruption phases The invention relates to a method for data transmission in a communication system, especially in a CDMA mobile radio system, wherein the data are transmitted structured into frames (1, 4, 5) and a transmitting station transmits the data in such a manner that ... | 08/22/2006 |
| 7062003 | Self-tuning baud rate generator for UART applications The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and does so without the use of phase-locked loop circuitry. The invention u... | 06/13/2006 |
| 7050518 | Data transmission method The invention relates to a method for the asynchronous serial data transmission between a transmitter and a receiver over a radio transmission link, whereby a synchronization data frame and a carrier recognition frame is arranged in front of the useful data frame. T... | 05/23/2006 |
| 7016303 | Transmitting method transmitting system and transmitter In a network of an IEEE 1394 system or the like, a data transmission rate can be properly controlled by an apparatus to receive the transmitted data. An apparatus for transmitting data is set as a first apparatus and each of one or more apparatus for receiving the t... | 03/21/2006 |
| 7003062 | Method and system for distribution of clock and frame synchronization information The present invention discloses a method and system for synchronizing processing modules. More specifically the present invention utilizes a master clock signal and associated synchronization information to coordinate the function dictated by packets within a synchr... | 02/21/2006 |
| 6965600 | Low speed modem transmission over packet networks A modem relay provides a local interface to the a modem on both ends of a call, demodulates the full duplex data stream, packetizes the bits for transport over an IP network, and remodulates the data stream at the remote end. The modem relay negotiates a best suppor... | 11/15/2005 |
| 6947414 | Device for emitting the response of a synchronous system to an asynchronous event An apparatus for immediately outputting a response of a synchronous system to an asynchronous event includes an advanced calculation device by means of which the responses of the synchronous system to possible asynchronous events can be calculated in advance. Also, ... | 09/20/2005 |
| 6944693 | Method for centrally setting data rate in a data transmission facility and a device for centrally setting data rates In the method according to the present invention for centrally setting data rate in a data transmission facility, the data rate is detected and set at subscribers on the basis of data rate setting telegrams sent by a central station. In addition to an interface to a... | 09/13/2005 |
| 6931029 | System and method for synchronizing with data received over an unreliable asynchronous medium A system for re-establishing synchrony with data that was synchronous data in a source device but for which synchrony is lost when the data is transmitted over an asynchronous and unreliable medium to a destination device. The system includes buffering of the data r... | 08/16/2005 |
| 6868134 | Method and apparatus for recovering a clock signal from an asynchronous data signal A clock recovery unit for generating a clock signal corresponding to an asynchronous data signal. The clock recovery unit includes an input port for receiving an incoming data signal; a local oscillator circuit for generating a plurality of clock signals having the ... | 03/15/2005 |
| 6714540 | Data communication method, communication frame generating method, and medium on which program for carrying out the methods are recorded A control portion A transmits only a transmission right to a control portion B. The control portion B receives the transmission right sent from the control portion A, obtains transmission-requested data B from a utilization portion B, and then transmits it with the ... | 03/30/2004 |
| 6704350 | AT-command analyzing device A first counter measures the span of the start bit of a first character of an AT command transmitted from a DTE based on instructions from an MPU. A decoder receives a measurement result of the first counter, outputs frequency-dividing data for producing ... | 03/09/2004 |
| 6677727 | Method of synchronizing communications means in a battery to communications means in an electronic device, an apparatus, and a battery Method and apparatus for synchronizing communication between a battery and an electronic device are disclosed. Bytes consisting of a number of bits are transmitted between the electronic device and the battery. A predetermined bit sequence is appended to ... | 01/13/2004 |
| 6611548 | Multipath processor A multipath processor processes a plurality of groups of spread-spectrum signals. Each group has a plurality of spread-spectrum signals. A first plurality of spread-spectrum signals is despread within a first group to generate a first plurality of desprea... | 08/26/2003 |
| 6587291 | Asynchronously sampling wide bi-phase codes Sampling data with wide bi-phase code symbols includes sampling a wide bi-phase code symbol in the data a number (N) of times to produce samples of data, selecting a subset of the samples, determining which sample in the subset of samples has a largest ma... | 07/01/2003 |
| 6549593 | Interface apparatus for interfacing data to a plurality of different clock domains Interface apparatus for interfacing data to a plurality of different clock domains where the clock signals in the different domains are phase locked together and respective clock signals have different frequencies includes a plurality of cascade connected... | 04/15/2003 |
| 6516420 | Data synchronizer using a parallel handshaking pipeline wherein validity indicators generate and send acknowledgement signals to a different clock domain A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. E... | 02/04/2003 |
