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| Number | Title | Issue Date |
| 8189725 | Loop bandwidth enhancement technique for a digital PLL and A HF divider that enables this technique A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the firs... | 05/29/2012 |
| 8180009 | Techniques for signaling reference signal parameters in a wireless communication system A technique for operating a wireless communication device includes assigning a reference signal bandwidth to a reference signal. Cyclic shift control bits (associated with the reference signal) are then allocated based on the assigned reference signal bandwidth. The... | 05/15/2012 |
| 8175206 | Communication apparatus There is provided a communication apparatus capable of reducing power consumption. The communication apparatus in accordance with the present invention includes a synchronization detection block 30 which detects synchronization by performing a receiving proce... | 05/08/2012 |
| 8144827 | Method for determining a residual frequency offset, communication system, method for transmitting a message, transmitter, method for processing a message and receiver A method of determining a residual frequency offset between a transmitter and a receiver in a transmission of data via a communication channel, is described, wherein the message is transmitted from the transmitter to the receiver via the communication channel and th... | 03/27/2012 |
| 8111796 | Method and system for switching between two (or more) reference signals for clock synchronization An apparatus and method is disclosed for synchronizing a timing signal for a computational system to different reference clock signals without impairing the operation of the computational system. A corresponding “offset” register is provided for each of the refe... | 02/07/2012 |
| 8073090 | Synchronous de-skew with programmable latency for multi-lane high speed serial interface A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training seque... | 12/06/2011 |
| 8073091 | Signal processing method and circuit to convert analog signal to digital signal A phase determination unit in a signal processing circuit generates sampling clocks with different phases in a clock generator and sequentially provides them to an analog-to-digital convertor. Then, the phase determination unit obtains differences between each adjac... | 12/06/2011 |
| 8019033 | Data transmission system, controller, and its method To provide a data transmission system capable of reducing skews between a reference signal and a phase modulation signal and accelerating data transmission. In a data transmission system having a transmitter for transmitting a reference signal and a phase mod... | 09/13/2011 |
| 8000428 | All-digital frequency synthesis with DCO gain calculation An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled osci... | 08/16/2011 |
| 7940876 | USB frequency synchronizing apparatus and method of synchronizing frequencies A universal series bus (USB) frequency synchronous apparatus using a start of frame (SOF) signal generated by a master device to mark a reference interval is disclosed. The frequency synchronizing apparatus includes a frequency divider, a counter unit with a default... | 05/10/2011 |
| 7912169 | Synchronization device and semiconductor device An apparatus for performing a channel-to-channel delay correction and frame synchronization with low latency includes, on each of a plurality of channels, a clock-and-data recovery circuit, a frequency divider circuit, a circuit for detecting the phase difference be... | 03/22/2011 |
| 7881418 | Device, method and program for detecting communication frame base point through blind processing A base point of a communication frame is detected by only using a reception signal, and an offset amount from the base point and the like are estimated. A device includes: an extraction unit for extracting self correlation processing signals from a digital communica... | 02/01/2011 |
| 7848473 | Phase interpolator having a phase jump A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation r... | 12/07/2010 |
| 7801259 | Frequency detecting circuit and method, and semiconductor apparatus including frequency detecting circuit A frequency detecting circuit and method and a semiconductor apparatus including the frequency detecting circuit, in which the frequency detecting circuit includes an edge detecting circuit, a clock signal generating circuit, and a determination circuit. The edge de... | 09/21/2010 |
| 7738615 | Sampling frequency conversion apparatus and signal switching apparatus A sampling frequency conversion apparatus having sampling frequency conversion circuits for a plurality of channels includes a detector detecting phase information of digital signals inputted to the conversion circuit for each channel, and an input section inputting... | 06/15/2010 |
| 7693245 | Frame-based carrier frequency and phase recovery system and method Header information is used to facilitate coarse frequency and frame recovery. The coarse frequency and frame recovery is thereafter utilized to perform adaptive phase and frequency synchronization on a frame-by-frame basis. A digitized signal representative of a wir... | 04/06/2010 |
| 7656982 | DSP-based data recovery A bit clock recovery apparatus for digital storage readout employing sync frames, where an oversampled readout signal is stored in memory, sync patterns are located in the signal using DSP means, distances of consecutive sync pattern locations are calculated, and bi... | 02/02/2010 |
| 7634034 | Payload boundary detection during multiband receiver synchronization Detecting a boundary within a transmitted packet is disclosed. A first symbol of the transmitted packet is received in a band. A second symbol of the transmitted packet is received in the band. The first and second symbols are compared. The boundary within the trans... | 12/15/2009 |
| 7627068 | Apparatus for frequency synchronization and method for the same An apparatus and method for frequency synchronization is proposed to obtain the pilot tones and evaluate the frequency offset and time offset for frequency synchronization. The frequency synchronization method has the following steps: filtering a baseband signal of ... | 12/01/2009 |
| 7627067 | Maximum likelihood synchronization for a communications system using a pilot symbol A method and apparatus for detecting and synchronizing packets of data with a repeated sequence as a pilot symbol received by a communications system are provided. The method and apparatus include receiving data, detecting a packet within the received data, producin... | 12/01/2009 |
| 7623610 | Method for determining QPSK modulation sequence of a downlink synchronization code A method is provided for determining the modulation sequence of the downlink synchronization codes. The method comprises: the method comprises a three step process: step one is to measure the phase of the downlink synchronization code. Step two is to generate an acc... | 11/24/2009 |
| 7593497 | Method and apparatus for adjustment of synchronous clock signals A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous... | 09/22/2009 |
| 7577223 | Multiplexed RF isolator circuit An integrated circuit isolator for providing data transfer of digital data signals across a voltage isolation barrier includes an integrated circuit package having a first plurality of input data pins on one side of the isolation barrier and a corresponding pluralit... | 08/18/2009 |
| 7436759 | Reception apparatus and method, and channel response measurement apparatus for receiving an orthogonal frequency divisional multiplexing signal A reception apparatus for receiving an OFDM signal having a plurality of pilot carriers that transmit predetermined pilot signals at predetermined symbols. The reception apparatus transforms the received OFDM signal to a frequency-domain OFDM signal, determines chan... | 10/14/2008 |
| 7433440 | Jitter-detecting circuit, receiving circuit including the jitter-detecting circuit, and communication system To provide a method for making a receiving-sensitivity control parameter for deciding the receiving sensitivity of an optical receiving circuit automatically follow the optimum position by using the jitter value of a binary-equalizing-data signal obtained by binary-... | 10/07/2008 |
| 7433394 | Transmitting/receiving arrangement, and a method for bidirectional transmission of data via a digital interface in a radio A transmitting/receiving arrangement comprises a baseband module (1) and a radio-frequency module (3), which are connected to one another via a bidirectional data line (21) and a bit clock line (22) of a digital interface (2). In o... | 10/07/2008 |
| 7433437 | Method for establishing a communication link A user equipment (UE) for establishing a communication link comprising a first module for processing a received communication signal and generating an index value associated with a primary synchronization code within said communication signal; a second module for ge... | 10/07/2008 |
| 7424046 | Spread spectrum clock signal generation system and method A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spe... | 09/09/2008 |
| 7424076 | System and method for providing synchronization information to a receiver The invention provides a method and system for synchronizing a transmitter and a receiver wherein the transmitter generates phase difference information indicating a phase difference between an internal and an external clock, the phase difference information is tran... | 09/09/2008 |
| 7415082 | Receiver including synch pulse detection and associated method A receiver includes a matched filter matched to a synch pulse and generates a matched filter output signal having peaks and valleys with one of the peaks corresponding to the synch pulse. An orthogonal filter is inversely matched to the synch pulse and generates an ... | 08/19/2008 |
| 7415044 | Remote synchronization in packet-switched networks Remote frequency synchronization is achieved between two or more nodes in a packet-switched network using differential timestamps. A line is fit to multiple differential time values using a minimum delay principle. Frequency synchronization and/or absolute time sync... | 08/19/2008 |
| 7409020 | Technique for filter-enhanced clock synchronization A technique for filter-enhanced clock synchronization is disclosed. In one particular exemplary embodiment, the technique may be realized by/as a method for filter-enhanced clock synchronization. The method comprises subjecting a clock error signal to a first expone... | 08/05/2008 |
| 7409029 | Transmission device for automatically set an optimal point for a signal decision making There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynami... | 08/05/2008 |
| 7409024 | Process for providing a pilot aided phase synchronization of carrier A process for providing a phase synchronization of a pilot aided carrier of an input digital signal z(k), the signal z(k) having signal fields of Ls symbol signals, namely a block of LP pilot symbol signals ZP(k) and a dat... | 08/05/2008 |
| 7398411 | Self-calibrating time code generator Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a phase-locked loop configured to provide a generated output signal based on a pha... | 07/08/2008 |
| 7386082 | Method and related apparatus for searching the syncword of a next frame in an encoded digital signal A method and apparatus for searching the synchronization signal of a next frame in encoded digital signal without the need of referring to a frame length indication signal. The encoded digital signal contains a plurality of frames, wherein each frame may have varyin... | 06/10/2008 |
| 7382846 | Off-symbol correlation technique A method of correlating a signal to a synchronization pattern is disclosed. The signal has a waveform with frequency and phase angle components that may be varied, at each repeated signal pulse, to communicate a change in a bit pattern of the signal. A synchronizati... | 06/03/2008 |
| 7376194 | Method and apparatus for compensating for residual frequency offset in an OFDM system Disclosed is a method for compensating for a residual frequency offset in an orthogonal frequency division multiplexing system comprising the steps of: a) performing a fast fourier transform for an input signal to convert the input signal into a serial signal; b) de... | 05/20/2008 |
| 7372928 | Method and system of cycle slip framing in a deserializer A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit s... | 05/13/2008 |
| 7372875 | Systems and methods for synchronization in asynchronous transport networks Techniques for synchronizing the clock of a local telecommunications network connected to a remote clock source through an asynchronous transport network such as an Ethernet metropolitan area transport network. A basic holdover loop for retaining the current reconst... | 05/13/2008 |
