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| Number | Title | Issue Date |
| 7894562 | Data message sync pattern Data message sync patterns for use in a network that utilizes Manchester (Bi-Phase) signal encoding with an embedded sync pattern. The sync pattern of the invention differs from conventional sync patterns for Manchester (Bi-Phase) type signal encoding, allowing grea... | 02/22/2011 |
| 7564936 | Process and electronic decoding circuit for a diphase asynchronous frame whose length is not known in advance, corresponding application, computer programme and storage means A decoding process, by an electronic circuit of a diphase asynchronous frame carried by an encoded data signal and comprising L information bits followed by at least one stop bit. The process comprises a step for automatically detecting the length L in information b... | 07/21/2009 |
| 7415072 | Drive control for an electric drive with a secure electrical separation of power element and control element The invention relates to a drive control for an electric drive with a secure electrical separation of power element and control element. The aim of the invention is to reduce the number of components such as optic couplers and buffer amplifiers between the power ele... | 08/19/2008 |
| 7397879 | Data communication method and data communication device and semiconductor device The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method include... | 07/08/2008 |
| 7397878 | Data communication method and data communication device and semiconductor device The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method include... | 07/08/2008 |
| 7382845 | Distribution of synchronization in an ethernet local area network environment Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data transmission burst includes: recovering a clock during the data transmission... | 06/03/2008 |
| 7376208 | Reception method for packetized information with automatic repeat request A decoding method is carried out in a receiver configured to accept format information relating to sequences of input data, to use format information in the decoding of each input sequence, and to issue an acknowledgement signal in the event that an input sequence i... | 05/20/2008 |
| 7369067 | Optical coupled type isolation circuit In an optical coupled isolation circuit, a PWM encoder encodes a one-bit binary data signal supplied from a sigma-delta analog-digital converter in synchronization with a clock signal of a cycle T to produce a pulse width modulation signal. The pulse width modulatio... | 05/06/2008 |
| 7362536 | Disk drive that compensates for phase incoherence between radially adjacent servo tracks and methods thereof Methods of compensating for radial incoherence in servo information that is read from adjacent servo tracks that have a phase offset relative to one another on a data storage disk of a disk drive are provided. While a transducer is seeking to a target track, the tra... | 04/22/2008 |
| 7359471 | Data communication method and data communication device and semiconductor device The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method include... | 04/15/2008 |
| 7359472 | Method and apparatus for wireless data transmission A method and apparatus for wireless data transmission between a base station and one or more, in particular, passive and/or backscatter-based transponders, in which the base station modulates a carrier signal with a modulation signal, to generate synchronization mar... | 04/15/2008 |
| 7356077 | Method and apparatus for testing network integrity Apparatuses and methods for testing the integrity of high speed optical fiber transmission networks are presented. Data from an optical network, for example, NRZ formatted data at forty gigabits per second and higher may be reliably recovered using embodiments of th... | 04/08/2008 |
| 7356106 | Clock and data recovery circuit A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects frequency difference between the output signals of the PD and QP detector and... | 04/08/2008 |
| 7352771 | Data collision detection device and method A data collision detection device that includes a means for de-modulating at least one carrier signal corresponding to a received modulated subcarrier signal from at least one data transmitter to recover the subcarrier signal from the carrier signal. A microcontroll... | 04/01/2008 |
| 7342519 | Receiving device and tire pressure monitoring system A receiving device is provided. A pulse width is measured, it is selected whether a determination process is performed for a pulse width having the length of one bit in accordance with the measured value of the pulse width or a pulse width having the length of ½ bi... | 03/11/2008 |
| 7327992 | Tracking generator with internal vector modulation source A tracking generator for an RF measurement instrument having a receiver and a controller includes a vector modulator internal to the tracking generator. The internal vector modulator modulates complex baseband signals based on data from the controller to produce a v... | 02/05/2008 |
| 7321647 | Clock extracting circuit and clock extracting method In a clock extracting circuit according to the present invention, after serial data is subjected to oversampling using a reference clock of 2N times a frequency of the serial data, clock timing in a period of time in which signal level remains unchanged for a long d... | 01/22/2008 |
| 7319722 | Circuit for the decoding of biphase signals A decoding circuit and associated method are provided for decoding a biphase signal. The decoding circuit may include a precharging register to precharge a pair of states of the biphase signal, where a state of the pair of states is precharged at each pulse of a per... | 01/15/2008 |
| 7289589 | Maximum likelihood bit synchronizer and data detector A bit synchronizer (16) that includes a tapped delay line (38) connected to a plurality of timing hypothesis circuits. A control and adjudication circuit (50) is connected to the timing hypothesis circuits, and compares outputs of the timing hyp... | 10/30/2007 |
| 7272201 | System for synchronous sampling and time-of-day clocking using an encoded time signal The system for synchronous sampling uses an encoded time signal, such as an IRIG-B signal. The IRIG-B signal is applied to an edge detector, which produces pulses based on the edges of the encoded time signal. These signals are applied to a phase-locked-loop assembl... | 09/18/2007 |
| 7272358 | Channelization scheme for wireless local area networks A four channel wireless network channelization scheme is described that is particularly usable in the ISM frequency band between 2400 MHz and 2483.5 MHz. The preferred channelization scheme permits access points to be set at one of four frequencies in the ISM band, ... | 09/18/2007 |
| 7263138 | Q-quenching super-regenerative receiver A super-regenerative receiver uses controlled Q-quenching and may limit the resonant tank circuit amplitude by loading the tank circuit as soon as regenerative oscillation is detected. An amplitude detector is coupled to the regenerative amplifier and controls a Q l... | 08/28/2007 |
| 7260164 | Efficient filtering of RxLOS signal in SerDes applications An efficient filter circuit and method for filtering a loss of receiver signal prevents false signals caused by glitches. The short glitches that happen at the positive edge of the clock signal may be prevented from affecting the whole clock cycle. The false signal ... | 08/21/2007 |
| 7260106 | Method and apparatus for managing energy usage of processors while executing protocol state machines A method and apparatus of implementing protocol state machines that conserve energy on energy conscious devices is disclosed. Under this method, most of the energy consuming protocol state machine context invocations or operations are aggregated in time and are sche... | 08/21/2007 |
| 7254198 | Receiver system having analog pre-filter and digital equalizer A receiver system suitable for a local area network contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605). A symbol-information-carrying input analog signal... | 08/07/2007 |
| 7248658 | Method and circuit for deriving a second clock signal from a first clock signal A clock generation circuit for a dual system radio frequency station is provided. The station includes a digital synthesis circuit clocked by a first clock signal for a first RF system that is adapted to generate a base signal output of a predetermined frequency. A ... | 07/24/2007 |
| 7224297 | Compressing log files Data is compressed, which includes first through sixth patterns having respective first through sixth values, where the first pattern precedes the second pattern in the data, the third pattern precedes the fourth pattern in the data, and the fifth pattern precedes t... | 05/29/2007 |
| 7206146 | Biphase magnetic pattern detector using multiple matched filters for hard disk drive A hard disk drive (HDD) holds data using a biphase scheme. A plurality of matched filters are used to detect binary data represented by the biphase pattern without the need for synchronous sampling or equalization. ... | 04/17/2007 |
| 7206563 | Reduction of radio frequency interference (RFI) produced by switching amplifiers Apparatus and methods for reducing radio frequency interference produced by switching amplifiers, includes a variable-order noise shaper in a system that includes an AM tuner. An alternative implementation involves determining the tuned frequency of a radio signal. ... | 04/17/2007 |
| 7203240 | Method of recovering clock signal using user clock code in TDM digital video signal and transmitting/receiving apparatus used for the method A clock recovery method for a TDM digital video signal and a transmitting/receiving apparatus for the clock recovery method are disclosed. A transmitter inserts a user clock code containing a predetermined number of points into the digital video signal during TDM pr... | 04/10/2007 |
| 7203023 | Magnetic recording unit and magnetic recording medium The present invention provides a magnetic recording unit, including: a magnetic head; a magnetic recording medium having a servo pattern for adjusting a position of the magnetic head; a frequency detecting element for detecting a frequency in the servo pattern on a ... | 04/10/2007 |
| 7161992 | Transition encoded dynamic bus circuit A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. ... | 01/09/2007 |
| 7153047 | Systematic lenticular lens selection in a digital printing environment Disclosed herein is a method for determining a lenticular lens resolution for use in digital press printing. The method includes determining a digital press machine resolution d, setting a master interlaced image resolution m for a master interlaced image such that ... | 12/26/2006 |
| 7151811 | Electric circuit for decoding a two-phase asynchronous data signal and corresponding decoding method, device for controlling equipment This invention relates to an electronic circuit for decoding an asynchronous two-phase data signal. According to the invention, such an electronic circuit comprises means for generating a decoding clock using a counter powered by an internal clock, and repeat... | 12/19/2006 |
| 7145850 | Optical disc recording apparatus and control method therefor A phase difference detection circuit (270) and a gain adjusting circuit (280) are provided in an optical disc recording apparatus (200). When the phase difference detection circuit detects a phase difference between an ATIP synchronization signa... | 12/05/2006 |
| 7143312 | Alignment of recovered clock with data signal A recovered clock signal is aligned (“eye centered”) with a data signal from which it is recovered by intentionally varying one of the factors or parameters that causes misalignment. For example, if a loop circuit (i.e., a phase-locked loop or a delay-locked loo... | 11/28/2006 |
| 7136446 | Method and apparatus for data and clock recovery in a biphase-coded data signal A method and apparatus for data and clock recovery in a biphase-coded data signal is described, in which the data signal is sampled using a sampling frequency that is greater than twice the bit frequency of the data signal. The bit limits of the data signal are then... | 11/14/2006 |
| 7133482 | Decoding method and Manchester decoder A method and a corresponding decoder for decoding a Manchester encoded binary data signal includes receiving the Manchester encoded binary data signal having a first sequence of central bit transitions and a second sequence of initial bit transitions. A local clock ... | 11/07/2006 |
| 7123897 | Directional receiver coupling arrangement with frequency selectivity and gain control for DSL A directional coupler for a modem has a high common mode noise rejection characteristic with low transmit signal leakage, and reduced distortion of components mixed with a received signal. A primary filter network is connected to a communications circuit. The primar... | 10/17/2006 |
| 7114084 | Data controlled programmable power supply A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “z... | 09/26/2006 |
