Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 8130890 | Semiconductor memory device having data clock training circuit A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a m... | 03/06/2012 |
| 8130889 | Receive timing manager A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to se... | 03/06/2012 |
| 8081725 | Edge evaluation of ASK-modulated signals Signal processing circuit including a demodulator that receives a receive signal with signal edges, and outputs a demodulated receive signal with transitions from a first level to a second level or vice versa at signal edges of the receive signal, wherein points of ... | 12/20/2011 |
| 8077820 | Detection of frequency correction bursts and the like In one embodiment, a frequency correction (FC) burst is detected in a complex signal received by a mobile station of a GSM/EDGE wireless communications network by applying the complex signal to one or more correlation paths of a burst detector within the mobile stat... | 12/13/2011 |
| 8014483 | Method of acquiring initial synchronization in impulse wireless communication and receiver A receiver in an impulse wireless communication. The receiver (300) includes a pulse-pair correlator (304) that receives a signal (316) and divides it into two signals for paths. One of the signals is input to signal multiplier (312) whil... | 09/06/2011 |
| 8009784 | Clock embedded differential data receiving system for ternary lines differential signaling A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a ... | 08/30/2011 |
| 7970091 | Method for reducing spectral regrowth in a spectrally efficient digital modulation scheme A method that uses time-domain processing on a spectrally efficient digital modulation scheme to reduce the bandwidth expansion in envelope elimination and restoration (EER) amplifiers is disclosed. The method identifies and localizes sections of the signal responsi... | 06/28/2011 |
| 7817762 | Method and apparatus for detecting leading pulse edges An apparatus and method for detecting leading pulse edges of a signal includes a controller, hysteresis threshold comparators and qualification timers. The controller uses the outputs from the timers in order to determine whether or not a transition of the input sig... | 10/19/2010 |
| 7778369 | Multi-carrier transmission device and multi-carrier transmission method There is provided a multi-carrier transmission device capable of improving a packet error ratio in a system where transmission data is repeatedly multi-carrier-transmitted. In this device, the transmission data is subjected to error correction encoding in an error c... | 08/17/2010 |
| 7760835 | Wireless communications devices, methods of processing a wireless communication signal, wireless communication synchronization methods and a radio frequency identification device communication method A wireless communication device includes an antenna configured to receive electromagnetic energy corresponding to a wireless communication signal outputted using an interrogator and to output electrical energy corresponding to the received electromagnetic energy, co... | 07/20/2010 |
| 7688926 | Frequency overlay communication system and control method thereof A frequency overlay communication system that includes a first communication system for performing communication using a first frequency band being a preset bandwidth; and a second communication system for performing communication using a second frequency band being... | 03/30/2010 |
| 7672416 | High-speed serial transceiver with sub-nominal rate operating mode A communication device comprises a receiver and a data recovery module. The receiver may be an element of a serial transceiver embedded in or otherwise associated with an FPGA or other type of reconfigurable hardware. The receiver is operable with an unlocked sampli... | 03/02/2010 |
| 7643597 | Methods for selecting a subsequence of video frames from a sequence of video frames A method for selecting a subsequence of video frames (72-84) from a sequence of video frames (70) comprising defining a distance function between video frames (72-84) in the sequence of video frames (70). An optimization cri... | 01/05/2010 |
| 7613265 | Systems, methods and computer program products for high speed data transfer using an external clock signal Systems, methods and computer program products for capturing data. The methods include receiving an external clock signal having a first frequency, a first edge and a second edge. A clock period of the external clock period is the amount of time between any two succ... | 11/03/2009 |
| 7505541 | NRZ/PAM-4/PRML triple mode phase and data detector The multi-mode phase and data detector includes a phase detector and a charge pump. A plurality of latching blocks clocked on complimentary phases of a feedback signal produces a plurality of phase and transition signals. Based on a selectable bias level, latched co... | 03/17/2009 |
| 7489754 | Frequency-lock detector A frequency-lock detector (FLD) adapted to register more than one target count per period of a target clock signal to generate a count value related to a frequency difference between the target clock signal and a reference clock signal. In various embodiments of the... | 02/10/2009 |
| 7477713 | method for providing automatic adaptation to frequency offsets in high speed serial links Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving... | 01/13/2009 |
| 7466783 | Method and system to implement a double data rate (DDR) interface Embodiments of the invention relate to a method and system to implement a DDR interface, such as a high-speed encode/decode interface. In one embodiment, a method of encoding data comprises the acts of (1) receiving a first signal, a second signal, and a first clock... | 12/16/2008 |
| 7453970 | Clock signal selecting apparatus and method that guarantee continuity of output clock signal Provided are a clock signal selecting apparatus and method that can guarantee the continuity of an output clock signal. The clock signal selecting apparatus and method can synchronize the phases of at least two clock signals by continuously controlling the phases of... | 11/18/2008 |
| 7434084 | Method and apparatus for eliminating sampling errors on a serial bus A synchronous bit-serial data interface utilizes a transmitter that transmits a data stream having duplicates of each data bit. The receiver samples the data stream utilizing either the rising or falling edge of a received clock signal. If the rising edge is utilize... | 10/07/2008 |
| 7424077 | Jitter sensitive maximum-sequence detection A channel detector has an anchor points inserter, a desired signal calculator, a distance calculator and a data detector. The anchor points inserter is adapted to choose values of expected transition locations for transition shifts within a received signal and to in... | 09/09/2008 |
| 7424046 | Spread spectrum clock signal generation system and method A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spe... | 09/09/2008 |
| 7424059 | Data transfer circuit A transmission unit loads transmission data on a first register and outputs it to a transfer line and starts counting the transmission clock signals in a strobe generation counter according to a transmission clock signal. When the counted value reaches a set value, ... | 09/09/2008 |
| 7421029 | Impulse response shortening and symbol synchronization in OFDM communication systems A method for receiving at a receiver having a variable filter a transmitted signal that includes a periodic training signal. The method includes (a) receiving and sampling the transmitted signal at the receiver to produce a digital complex baseband signal; (b) filte... | 09/02/2008 |
| 7415089 | High-speed serial link clock and data recovery A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The cloc... | 08/19/2008 |
| 7397879 | Data communication method and data communication device and semiconductor device The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method include... | 07/08/2008 |
| 7397878 | Data communication method and data communication device and semiconductor device The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method include... | 07/08/2008 |
| 7397876 | Methods and arrangements for link power reduction Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by ... | 07/08/2008 |
| 7382845 | Distribution of synchronization in an ethernet local area network environment Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data transmission burst includes: recovering a clock during the data transmission... | 06/03/2008 |
| 7372931 | Unit interval discovery for a bus receiver A bus data signal is applied to a tapped data delay line. The various increasingly delayed data values present at the taps of the delay line are clocked into respective cells of a sticky ZEROs register (SZERO) previously initialized to all ONES, and into respective ... | 05/13/2008 |
| 7366141 | Cell search method and apparatus in a WCDMA system A cell search method for use in a mobile communication system, the method including: performing one or more identification steps for identifying timing and codes of oversampled input signals; and reducing the resolution of the oversampled input signals before perfor... | 04/29/2008 |
| 7362837 | Method and apparatus for clock deskew A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset. Bit error measurements are made at each sampling point in time and compared. Bit error measurements may be made by comparing received data to ... | 04/22/2008 |
| 7362374 | Video interlacing using object motion estimation One embodiment disclosed relates to the use of object motion estimation to interlace a progressive video sequence. One of a plurality of consecutive frames is segmented and motion vectors for each segment are determined though object motion estimation. Interpolated ... | 04/22/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7359471 | Data communication method and data communication device and semiconductor device The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method include... | 04/15/2008 |
| 7356108 | OFDM receiver having adaptive channel estimator for correcting channel fading based on accumulated pseudo power values A channel estimator is configured for determining a gain adjustment for a received wireless signal having a prescribed plurality of tones. The channel estimator is configured for generating, for each of the tones, a corresponding pseudo power value representing a de... | 04/08/2008 |
| 7356106 | Clock and data recovery circuit A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects frequency difference between the output signals of the PD and QP detector and... | 04/08/2008 |
| 7352771 | Data collision detection device and method A data collision detection device that includes a means for de-modulating at least one carrier signal corresponding to a received modulated subcarrier signal from at least one data transmitter to recover the subcarrier signal from the carrier signal. A microcontroll... | 04/01/2008 |
| 7349510 | Apparatus for data recovery in a synchronous chip-to-chip system An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing refe... | 03/25/2008 |
| 7349509 | Multi rate clock data recovery based on multi sampling technique A clock and data recovery device (CDR) based on multi-rate multi-phase oversampling technique is capable of receiving serial data streams of different data rates. The CDR uses a multi-rate multi-phase oversampling technique. N phase shifted clocks are generated base... | 03/25/2008 |
