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| Number | Title | Issue Date |
| 8184758 | Method and apparatus for detecting electrical idle A system and method for detecting electrical idle in a receiver is disclosed herein. A receiver includes a differential receiver, an analog idle detector, and a first filter. The differential receiver receives a variable rate differential signal. The analog idle det... | 05/22/2012 |
| 8180008 | Single wire transmission without clock synchronization The present invention discloses a method for single-wire transmission without clock synchronization, comprising: providing three states; defining a spacing bit by a first state of the three states; and defining data signals, a start signal and an end signal by combi... | 05/15/2012 |
| 8170168 | Clock data recovery circuit A simple circuit that supports high and low data rates is provided. The circuit includes: a detection circuit 11 for detecting whether D1≠D2 or D1≠D3, assuming that logical values of an input data signal DATAIN sampled at timin... | 05/01/2012 |
| 8073089 | Data player and data play method A synchronous pattern detection section checks coincidence between a predetermined reference synchronous pattern and a bit pattern included in a data stream. Each time a bit pattern which coincides with the reference synchronous pattern is detected, the synchronous ... | 12/06/2011 |
| 7995693 | Method and apparatus for serial communication using clock-embedded signals Apparatus for serial communication using embedded clock signals includes a data divider for dividing a data stream into odd-numbered and even-numbered data streams; a clock-embedded signal generator for generating odd-numbered and even-numbered embedded clock signal... | 08/09/2011 |
| 7991101 | Multiple channel synchronized clock generation scheme Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deseriali... | 08/02/2011 |
| 7991100 | Method for the synchronization of a radio receiver, and adapted receiver for the implementation of said method A method for the synchronization of a radio receiver, comprising an estimation of the moment when a pulse (11, 17) is received (11, 17), performed from the moment when a previous pulse was received. The estimated moment is compared with the real moment... | 08/02/2011 |
| 7970090 | Method and apparatus for a self-synchronizing system A self-synchronizing system that provides a master system component and a master clock source to provide a stable timing reference to the master system component. Timing information is then propagated throughout the system via encoded transmissions containing the ti... | 06/28/2011 |
| 7924962 | Clock regeneration circuit technical field Clock synchronization resistance is improved against selectivity fading without degrading the stability of clock phase synchronization control. Clock phase detector 7, which forms part of a clock reproduction PLL, is preceded by orthogonal component equalizer... | 04/12/2011 |
| 7844020 | Transmission system, transmitter, receiver, and transmission method There is provided a transmission system in which a data sequence is transmitted. The transmission system includes a transmitter that generates a transmission signal by converting pieces of data included in the data sequence into data waveforms each of which has (i) ... | 11/30/2010 |
| 7680228 | Communication system, real-time control device, and information processing system In addition to fast on-off timing, instructive information on an output wave such as an amplitude or a slope is transmitted through a small number of signal lines. Output wave modifier information such as the amplitude or slope is transferred through serial communic... | 03/16/2010 |
| 7599457 | Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phas... | 10/06/2009 |
| 7555087 | Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that ... | 06/30/2009 |
| 7477712 | Adaptable data path for synchronous data transfer between clock domains Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A contr... | 01/13/2009 |
| 7436918 | Output stage synchronization Systems and methods for transferring data across clock domains in a manner that avoids metastability of the data and is very tolerant of variations in the clock signals of the different clock domains. One embodiment of the invention comprises a mechanism for passing... | 10/14/2008 |
| 7424078 | Synchronous compensator adaptively defining an enable range for synchronous compensation In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable signal from a synchronous compensator circuit, thereby excluding the ... | 09/09/2008 |
| 7424046 | Spread spectrum clock signal generation system and method A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spe... | 09/09/2008 |
| 7409020 | Technique for filter-enhanced clock synchronization A technique for filter-enhanced clock synchronization is disclosed. In one particular exemplary embodiment, the technique may be realized by/as a method for filter-enhanced clock synchronization. The method comprises subjecting a clock error signal to a first expone... | 08/05/2008 |
| 7398411 | Self-calibrating time code generator Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a phase-locked loop configured to provide a generated output signal based on a pha... | 07/08/2008 |
| 7382845 | Distribution of synchronization in an ethernet local area network environment Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data transmission burst includes: recovering a clock during the data transmission... | 06/03/2008 |
| 7366267 | Clock data recovery with double edge clocking based phase detector and serializer/deserializer A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholl... | 04/29/2008 |
| 7366206 | Multi-media jitter removal in an asynchronous digital home network A method and an apparatus using a system level clocking scheme to remove jitter from multi-media packets distributed over an asynchronous network. The present invention overcomes the problems associated with jitter introduced in an asynchronous network by using vari... | 04/29/2008 |
| 7366271 | Clock and data recovery device coping with variable data rates A clock and data recovery (CDR) device is disclosed that is capable of recovering a clock signal from a data signal that has a variable data rate. The CDR device includes a reference clock generating section for dividing a basic clock by a first predetermined value ... | 04/29/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7352835 | Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that ... | 04/01/2008 |
| 7342953 | Synchronization detection circuit A synchronization detection circuit includes: a matched filter 105 for outputting a correlation value, between a spreading code and data that is obtained by sampling a code spread signal 101, using a sampling clock for one chip cycle; a sampling clock ... | 03/11/2008 |
| 7330459 | MAC controller and clock synchronizing method for use with the same In a wireless local area network media access controller (MAC) disposed in a first node of a wireless local area network, a method is performed to synchronize the clock of the first node with the clock of a second node in the wireless local area network. When a requ... | 02/12/2008 |
| 7317489 | Teletext data detection by data content based synchronization and error reduction A technique to provide a cost effective solution to detect teletext data that can reduce detected error in teletext when the transmission data rate is known. In one example embodiment, this is accomplished by detecting data bits in an unsynchronized digital data str... | 01/08/2008 |
| 7298800 | Analog signal control method, analog signal controller, and automatic gain controller An analog signal control method for accurately controlling an analog signal irrespective of a latency. The analog signal control method includes the steps of converting the analog signal to a digital signal, performing an arithmetic processing of the digital signal ... | 11/20/2007 |
| 7288969 | Zero clock delay metastability filtering circuit A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge ... | 10/30/2007 |
| 7278071 | Receiving circuit for receiving message signals The invention relates to a receiving circuit for receiving message signals, having a sampler for converting the message signal into a sampled signal, an analyzing unit for decoding the sampled signal and checking it for errors, and a control unit for controlling the... | 10/02/2007 |
| 7275174 | Self-aligning data path converter for multiple clock systems A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (... | 09/25/2007 |
| 7274230 | System and method for clockless data recovery A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating two or more parallel data streams from the serial data stream. One o... | 09/25/2007 |
| 7272202 | Communication system and method for generating slave clocks and sample clocks at the source and destination ports of a synchronous network using the network frame rate A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or diff... | 09/18/2007 |
| 7265690 | Simplified data recovery from high speed encoded data The present invention facilitates data recovery without requiring selection of a sample phase. The data is recovered by sampling a received signal to obtain a number of samples at a number of phases over a given time period referred to as a bit time. The samples are... | 09/04/2007 |
| 7263150 | Probability estimating apparatus and method for peak-to-peak clock skews A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for estimating the generation probability of the peak-to-peak value or peak val... | 08/28/2007 |
| 7260164 | Efficient filtering of RxLOS signal in SerDes applications An efficient filter circuit and method for filtering a loss of receiver signal prevents false signals caused by glitches. The short glitches that happen at the positive edge of the clock signal may be prevented from affecting the whole clock cycle. The false signal ... | 08/21/2007 |
| 7256635 | Low lock time delay locked loops using time cycle suppressor The invention discloses a delay locked loop (DLL) architecture with a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppr... | 08/14/2007 |
| 7254203 | Method and apparatus for use of high sampling frequency A/D converters for low frequency sampling A method and apparatus for adding fill-in clock pulses to an analog to digital converters input clock signal between requests for analog data acquisition. The circuit that provides the fill-in clock pulses is able to detect a request for analog data acquisition, syn... | 08/07/2007 |
| 7245683 | System and methods of recovering a clock from NRZ data A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may be received in differential form (i.e., a separate NRZ signal and an i... | 07/17/2007 |
