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| Number | Title | Issue Date |
| 8189724 | Closed loop power normalized timing recovery for 8 VSB modulated signals A timing recovery loop includes a sampler, a narrow band filter, an RMS normalizer, a timing error detector, and a sample controller. The sampler samples a received signal. The narrow band filter filters the sampled received signal so as to pass an upper band edge o... | 05/29/2012 |
| 8184756 | Symbol timing acquisition using early-late interpolation Symbol timing acquisition is described for a wireless broadband signal received at a user terminal from a gateway via a satellite. In-phase and quadrature channels of the wireless signal may each be sampled at a rate of one sample per symbol. The samples may be inte... | 05/22/2012 |
| 8184757 | Pattern agnostic on-die scope An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a rec... | 05/22/2012 |
| 8180007 | Method for clock and data recovery An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phase... | 05/15/2012 |
| 8165254 | Apparatus and method for receiving signal for extent limitation of timing synchronization in MB-OFDM UWB system The present invention relates to an apparatus and a method for receiving signal for extent of timing synchronization in MB-OFDM UWB System. The invention divides the digital samples completed of sampling twice as much as minimum sampling clock required to restore th... | 04/24/2012 |
| 8165255 | Multirate resampling and filtering system and method A discrete time signal resampling circuit (200). A data sample processing module (260) removes selected samples from a sequential plurality of discrete time signal samples to implement fractional resampling where the data sample processing module store... | 04/24/2012 |
| 8160194 | Sampling method, reconstruction method, and device for sampling and/or reconstructing signals Reconstruction method for reconstructing a first signal (x(t)) regularly sampled at a sub-Nyquist rate, comprising the step of retrieving from the regularly spaced sampled values (ys[n], y(nT)) a set of weights (cn, cnr, ck | 04/17/2012 |
| 8155256 | Method and apparatus for asynchronous clock retiming A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two ... | 04/10/2012 |
| 8149974 | Phase comparator, phase comparison device, and clock data recovery system A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the compariso... | 04/03/2012 |
| 8149975 | Method and computer program for identifying a transition in a phase-shift keying or frequency-shift keying signal A system for identifying at least one phase transition in a phase-shift keying signal comprising a plurality of data samples corresponding to phase values. The system comprises a memory operable to store computing device executable instructions; and a computing devi... | 04/03/2012 |
| 8139696 | Baud rate detection A method is provided of characterising a data stream of binary symbols, the method comprising sampling the stream at a predetermined rate sufficient to capture at least two samples per binary symbol, identifying the shortest continuous run of samples having the same... | 03/20/2012 |
| 8139697 | Sampling method and data recovery circuit using the same A sampling method and a data recovery circuit using the same are provided. The sampling method includes following steps. First, a first strobe, a second strobe, a third strobe, and a fourth strobe are provided, wherein the second strobe lags the first strobe a first... | 03/20/2012 |
| 8130887 | Method and arrangements for link power reduction Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by ... | 03/06/2012 |
| 8130888 | Calibrating a phase detector and analog-to-digital converter offset and gain The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner t... | 03/06/2012 |
| 8130886 | Samples of bandlimited signals recovery system and method A method and system of sample recovery is disclosed. In one embodiment, a method includes selecting initially in an arbitrary manner, a current symbol from a sequence of input samples, comparing a symbol timing estimate associated with the current symbol to a predet... | 03/06/2012 |
| 8126101 | Method and apparatus for varying a dynamic range A communications device comprises a receiver for receiving an input signal operably coupled to analogue to digital converter logic. The analogue to digital converter logic is operably coupled to control logic via a signal analyzer arranged to analyze a converted rec... | 02/28/2012 |
| 8121239 | Unidirectional sweep training for an interconnect In one embodiment, the present invention includes a receiver having a delay lock loop (DLL) to receive a clock signal and to generate a plurality of clock phases therefrom, and an offset controller including a first register set for a first phase interpolator and a ... | 02/21/2012 |
| 8121238 | System and method for synchronizing digital bits in a data stream A system and method for synchronizing a receiver of a bit stream to the bit stream include a correlator to remove the PN code modulation and to generate a stream of time sequence values (samples) from the received bits. A plurality of accumulators are included, each... | 02/21/2012 |
| 8121237 | Signaling system with adaptive timing calibration An integrated circuit device includes a delay circuit, sampling circuit and delay control circuit that cooperate to carry out adaptive timing calibration. The delay circuit generates a timing signal by delaying an aperiodic input signal for a first interval. The sam... | 02/21/2012 |
| 8116415 | Semiconductor integrated circuit, communication apparatus, information playback apparatus, image display apparatus, electronic apparatus, electronic control apparatus and mobile apparatus The semiconductor integrated circuit having a transmitter circuit for transmitting a supplied external data signal DIN. The transmitter circuit includes: a transmitter flip-flop circuit having a reference clock CK as an input for holding the external data signal DIN... | 02/14/2012 |
| 8111795 | Method and system for a multi-channel signal synchronizer Certain aspects of a multi-channel signal synchronizer may comprise receiving a plurality of clock signals from a plurality of clock signal sources, wherein a portion of the received plurality of clock signals may be out of synchronization with a remaining portion o... | 02/07/2012 |
| 8102959 | Digital audio processing system and method A digital audio processing system includes an input to receive a phase component of a signal. The digital audio processing system includes symbol recognition logic to adjust a sample of the phase component using an offset value. The symbol recognition logic maps the... | 01/24/2012 |
| 8098786 | Reception apparatus In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of... | 01/17/2012 |
| 8098785 | Signal processing circuit A signal processing circuit detects a pulsative change point of an input signal and sets a phase point which is shifted by a predetermined phase difference from the detected pulsative change point of the input signal as the timing for sampling the input signal. ... | 01/17/2012 |
| 8098784 | Systems, methods and computer program products for high speed data transfer using a plurality of external clock signals A method for capturing data includes receiving a plurality of external clock signals including a first external clock signal and a second external clock signal. Each external clock signal has a first frequency, a first edge and a second edge. Data is received on one... | 01/17/2012 |
| 8094766 | Tracker circuit and method for automated test equipment systems A digital data signal capture circuit for synchronization of received digital data signals includes a transition detector for determining a state transition of the received digital data signal. The transition detector samples the received digital data signal at a fi... | 01/10/2012 |
| 8081723 | Serial data signal eye width estimator methods and apparatus Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The fi... | 12/20/2011 |
| 8068572 | Self-timing method for adjustment of a sampling phase in an oversampling receiver and circuit This invention discloses a self-timing method for phase adjustment. An analog signal is digitized at a first and second phase with respect to the symbols comprised in an analog signal in order to obtain first and second quantized samples. Then a first counter out of... | 11/29/2011 |
| 8068573 | Phase dithered digital communications system The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for ea... | 11/29/2011 |
| 8064560 | Systems and methods for detecting a signal across multiple Nyquist bands Systems and methods for detecting a signal across multiple Nyquist bands. The systems include an analog to digital converter (ADC), a clock signal generator configured to output a sample clock signal to the ADC, and a processor configured to process sampled signals ... | 11/22/2011 |
| 8064559 | Clock control of transmission-signal processing devices in mobile radio terminal devices To support a plurality of different mobile radio standards in mobile radio terminal devices using a single system oscillator, a sampling rate converter converts the sampling rates from an input rate to an output rate and additionally outputs control information whic... | 11/22/2011 |
| 8054927 | Synchronous circuit and method for receiving data The present invention includes: a synchronous-word detecting unit receives a baseband received signal including a synchronous word and data for each frame, and detects whether or not the synchronous word is coincided with an expected value in the baseband received s... | 11/08/2011 |
| 8054926 | Clock and data recovery system and method for clock and data recovery based on a forward error correction The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sam... | 11/08/2011 |
| 8050371 | Method and system for compensating for the effect of phase drift in a data sampling clock A method and system for compensating for the effect of phase drift in a data sampling clock during data transfer between sub-systems of an electronic device. The sub-systems of the electronic device transfer data frame by frame. Each frame includes multiple data win... | 11/01/2011 |
| 8050372 | Clock-data recovery circuit, multi-port receiver including the same and associated methods A clock-data recovery circuit includes a plurality of input ports and a code generation circuit. The plurality of input ports generates sampling clock signals based on digital control codes and samples input data signals based on the sampling clock signals to genera... | 11/01/2011 |
| 8045664 | Clock data recovery device A clock/data recovery device 1 comprises a sampler 10, a detector 20, an offset determination part 30, a clock output part 40, and a DA converter 50. The phases of clock signals CK and CKX are adjusted so as to match with th... | 10/25/2011 |
| 8045663 | Circuit and method for removing skew in data transmitting/receiving system A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding... | 10/25/2011 |
| 8040990 | Method and apparatus for estimating sampling frequency offset, and sampling timing recovery loop including the apparatus An apparatus for estimating a sampling frequency offset includes a waveform characteristic extraction unit, a variation quantity calculation unit, and a SFO (sampling frequency offset) estimator. The waveform characteristic extraction unit extracts a waveform charac... | 10/18/2011 |
| 8040989 | System and method for sampling rate adjustment of digital radio receiver Methods and systems for adjusting a sampling rate of a digital radio receiver are disclosed that comprise the steps of receiving from a decoder a first frame of data having a first number of samples; determining at the digital radio receiver a phase difference betwe... | 10/18/2011 |
| 8031820 | Sampling method, reconstruction method, and device for sampling and/or reconstructing signals Reconstruction method for reconstructing a first signal (x(t)) regularly sampled at a sub-Nyquist rate, comprising the step of retrieving from the regularly spaced sampled values (ys[n], y(nT)) a set of weights (cn, cnr, ck | 10/04/2011 |
