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| Number | Title | Issue Date |
| 8111794 | Data synchronizer for synchronizing data and communication interface including the same According to one embodiment, a data hold module is configured to receive first data synchronized with a first clock signal on the basis of a second timing signal and output second data obtained by synchronizing the received first data with a second clock signal diff... | 02/07/2012 |
| 8107575 | Method and circuit for changing modes without dedicated control pin A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency i... | 01/31/2012 |
| 8102958 | Pilot scrambling enabling direct pilot sequence detection in initial acquisition in evolved UTRA A communications network and method thereof include a base station controller configured to provide a repetition period of a primary synchronization channel to be equal to a predetermined integer value times a scrambling code length of the scrambling code of a commo... | 01/24/2012 |
| 8098783 | Training pattern for a biased clock recovery tracking loop Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alig... | 01/17/2012 |
| 8094765 | Clock and mode signals controlling data communication in three states Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or sync... | 01/10/2012 |
| 8094764 | Variable time delay control structure for channel matching A cosite interference cancellation system is provided for improved rejection of a signal coupled from a transmission antenna into a local receive antenna in the presence of local multipath. The cosite interference cancellation system and associated method advantageo... | 01/10/2012 |
| 8090064 | Single loop frequency and phase detection In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is de... | 01/03/2012 |
| 8085891 | System and method for management of mobile device communication A system and method for managing mobile device communication in an enterprise includes a device management agent and a synchronization agent in the mobile device. Information about the status of the mobile device is collected by the device management agent and the s... | 12/27/2011 |
| 8064558 | Receiving apparatus A receiving apparatus includes a first receiver, a second receiver, a received signal synthesizer connected to the first and second receivers, a synchronizing signal synthesizer connected to the first and second receivers, and a synchronization detector connected to... | 11/22/2011 |
| 8064557 | Programmable synchronization unit for a signal receiver A programmable synchronizing unit for a signal receiver has a received data memory for buffering received data, a correlation value data memory for storing correlation values, a data path for correlating the received data with the correlation values, a result data m... | 11/22/2011 |
| 8059774 | Frequency lock detection A system and method are provided for detecting the frequency acquisition of a synthesized signal in a non-synchronous communications receiver. The method accepts a non-synchronous communication signal having an input data signaling frequency, and compares the input ... | 11/15/2011 |
| 8054925 | Method and apparatus for synchronizing a receiver Various embodiments generally relate to a method for synchronizing a receiver, said method including receiving a stream that includes a cyclic extension, estimating a size of the cyclic extension, extracting an amount of the stream according to the estimated size, a... | 11/08/2011 |
| 8045662 | Binary ripple counter sampling with adjustable delays The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate sampling regardless of: delay mismatch between the sampler... | 10/25/2011 |
| 8040988 | Transceiver with selectable data rate An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock ... | 10/18/2011 |
| 8036329 | Sychronization during anti-collision An RFID system comprises at least one reading device (1) and at least one transponder (2, 2′, 2″, 2′″), which are configured for non-contact communication by means of modulated electromagnetic signals (SS), which contain data and/or commands pa... | 10/11/2011 |
| 8031819 | Systems and methods for synchronizing an input signal Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output s... | 10/04/2011 |
| 8027420 | Apparatus and method for transferring a signal from a fast clock domain to a slow clock domain A circuit is provided for transferring a signal from a fast clock domain to a slow clock domain. The circuit includes a fast clock domain configured to receive an input signal and, responsively, transfer an intermediate signal. The circuit also a slow clock domain c... | 09/27/2011 |
| 8023604 | Encoded data transfer device and encoded data transferring method An encoded data transfer device (1) includes a JPEG compressing section (14) that converts image data to encoded data, a data buffer (15) that stores the encoded data from the JPEG compressing section (14), a stored data amount detecting ... | 09/20/2011 |
| 8023602 | Serial data communication apparatus and methods of using a single line Serial data communication methods and apparatus using a single line are provided. The data communication methods may include: setting a rising edge of a serial pulse signal so that a cycle of the serial pulse signal begins therefrom; setting a falling edge of the se... | 09/20/2011 |
| 8023603 | Interface circuit including a shift clock generator to generate a shift clock having different cycles according to data sequence of data string An interface circuit includes a detector to detect a particular pattern from a sequence of output data, a shift clock generator to change a cycle of a shift clock according to the detection result, a shift register section to change a data output width by the shift ... | 09/20/2011 |
| 8014479 | Method and system for communicating sub-synchronization signals using a phase rotator A system and method of communicating sub-synchronization information into a transmitted digital audio stream and extracting sub-synchronization information from a received digital audio stream is provided. The method includes the steps of having a transmitter introd... | 09/06/2011 |
| 8000425 | Methods and apparatus to provide clock resynchronization in communication networks Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled... | 08/16/2011 |
| 7995692 | Frame-synchronization method and device A frame synchronization method and device. The method determines the frame start position D. That position D is the same as a position of a window H sliding along the received frame Tr. For various possible positions of the window H and for various blocks... | 08/09/2011 |
| 7991094 | Method and apparatus for transmitting and receiving a timing correction message in a wireless communication system A method for transmitting a timing correction message in a wireless communication system, the method comprising, Generating the timing correction message comprising a 8-bit MessageID field and a 2-bit NumSectors field wherein, the NumSectors field indicates the numb... | 08/02/2011 |
| 7991093 | Analog/digital circuit A digital filter operates on the basis of a first clock having a first frequency. A stereo modulator operates on the basis of a second clock having a second frequency higher than the first frequency and being asynchronous. The stereo modulator performs a predetermin... | 08/02/2011 |
| 7983368 | Systems and arrangements for clock and data recovery in communications A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a... | 07/19/2011 |
| 7983369 | Circuit for outputting data of semiconductor memory apparatus A data output circuit of a semiconductor memory apparatus can include a clock synchronization unit (which is driven by a power supply voltage) that can be configured to receive data and output first synchronization data and second synchronization data in synchroniza... | 07/19/2011 |
| 7978800 | Circuit for converting a transponder controller chip output into an appropriate input signal for a host device A translation circuit for mediating between a fiber-optic controller chip and a host device. The translation circuit may be on a fiber-optic transponder. The controller chip includes a phase locked loop that outputs a short synchronization signal when a hunting freq... | 07/12/2011 |
| RE42538 | System and method for signal synchronization in a communication system A system and method for information content-independent synchronization with a received signal. A variable of the signal (e.g., average energy or magnitude) which is related to the energy distribution, is measured over a period of time. The signal's information bear... | 07/12/2011 |
| 7970086 | System and method for clock drift compensation A method for processing a signal includes monitoring an over-sampled signal to detect deviations in a number of fill samples, and providing an electronic delay adjustment to a signal path. If a deviation in the number of fill samples is detected, the electronic dela... | 06/28/2011 |
| 7965800 | Clock recovery apparatus A clock recovery apparatus for generating a recovery clock from received data may include, but is not limited to, first and second oscillators. The first oscillator generates a first signal having a first frequency. The first signal synchronizes with the received da... | 06/21/2011 |
| 7961828 | Sync bursts frequency offset compensation A method (500) and system for compensation of frequency offset between a first transceiver (102) and a second transceiver (104) in wireless communication are disclosed. The compensation of the frequency offset between two or more transceivers ( | 06/14/2011 |
| 7961829 | Low jitter clock recovery from a digital baseband data signal transmitted over a wireless medium A system and method of transmitting a data stream from a data source over a baseband wireless communication system to one or more receivers. The receivers simultaneously recover the data and clock signals of the original data stream from the wireless transmitted dat... | 06/14/2011 |
| 7953195 | System and method for digitizing bit synchronization in wireless communication This invention relates to a method and system for digitizing bit synchronization in wireless communication. The method comprises delaying at intervals an input signal sequence, which contains at least one path of input signals; multiplying each path of input signals... | 05/31/2011 |
| 7953194 | Handling video transition errors in video on demand streams A system, method, and apparatus for handling transition errors is presented herein. The transition errors include handling unreported time base discontinuities during trick mode transition, miscalculated time stamps during trick mode transition, erroneous sequence e... | 05/31/2011 |
| 7936853 | False frequency lock detector A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock sign... | 05/03/2011 |
| 7936854 | Method and system of cycle slip framing in a deserializer A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit s... | 05/03/2011 |
| 7924960 | Input/output data rate synchronization using first in first out data buffers A system includes a first buffer configured to receive data at a first rate, and output the data at a second rate. A processing module configured to receive the data from the first buffer at the second rate, convert the data into processed data, and output the proce... | 04/12/2011 |
| 7924959 | Data conversion system A data conversion system acquires samples of low frequency signal components of an applied analog signal at a first data conversion rate and samples of high frequency signal components of the applied analog signal at a second data conversion rate that is higher than... | 04/12/2011 |
| 7920663 | Using the AC mains as a reference for frequency comparison Adjusting a local frequency source is disclosed. A local frequency comparison data is compared with a received frequency comparison data, wherein the local frequency comparison data reflects a difference, if any, between a locally measured AC frequency and a frequen... | 04/05/2011 |
