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| Number | Title | Issue Date |
| 8107506 | Method and apparatus for reducing service impairment in link aggregation group A method and apparatus for reducing service impairment in a LAG are provided. The method includes: dividing a service packet into multiple service sub-flows, and allocating the multiple service sub-flows to all the physical ports averagely; after a new port is added... | 01/31/2012 |
| 7460565 | Data communications circuit with multi-stage multiplexing In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit n... | 12/02/2008 |
| 7400657 | System and method for transporting multiple client data signals via a single server signal Systems and methods for conveying multiple low-bit-rate data streams over a data transport medium which is configured to transport data in a single, high-bit-rate data stream. In one embodiment, a plurality of low-bit-rate signals are received and a corresponding da... | 07/15/2008 |
| 7379481 | Apparatus and method for automatic provisioning of SONET multiplexer An OC3 to three DS3 SONET multiplexer is provided employing a field programmable gate array and other components in a single Type 400 mechanics card to achieve a form factor that is substantially reduced when compared to existing SONET multiplexers. The OC3 to three... | 05/27/2008 |
| 7349450 | Multi-stage high speed bit stream demultiplexer chip set having switchable master/slave relationship A bit stream demultiplexer that couples a high-speed bit stream media to a communication Application Specific Integrated Circuit (ASIC). The bit stream multiplexer performs its demultiplexing function staged within at least two integrated circuits. The first Integra... | 03/25/2008 |
| 7313660 | Data stream frequency reduction and/or phase shift A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of t... | 12/25/2007 |
| 7302505 | Receiver multi-protocol interface and applications thereof A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a second formatted input signal to produce an amplified input signal. The... | 11/27/2007 |
| 7098845 | Apparatus for generating an integrator timing reference from a local oscillator signal A receiver circuit including an oscillator, a mixer coupled to the oscillator, a switch coupled to an output of the mixer, and an envelope detector coupled to the oscillator, such that the envelope detector generates a timing signal for actuating the switch based on... | 08/29/2006 |
| 7095711 | Communication method and apparatus for a radio local area network system using macrodiversity A communication method for a radio LAN system provides communication at a first transmission rate. In the method, a first signal of the first transmission rate is time-divisionally distributed into n−1 second signals (n=3, 4, . . . ). The n−1 second signals are ... | 08/22/2006 |
| 7079555 | Integrated digital loop carrier system with virtual tributary mapper circuit An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders an to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digita... | 07/18/2006 |
| 7024685 | Transport demultiplexor with bit maskable filter The preferred embodiment of the present invention provides an improved transport demultiplexor that can receive and filter different data types before sending the data to system memory. The preferred embodiment provides a string comparator to facilitate real time fi... | 04/04/2006 |
| 7016344 | Time slot interchanging of time slots from multiple SONET signals without first passing the signals through pointer processors to synchronize them to a common clock A SONET multiplexed system architecture that permits greater levels of integration. The architecture includes a time slot interchanger for routing information from at least one SONET input signal path associated with a respective first time slot to at least one SONE... | 03/21/2006 |
| 7002986 | Mapping arbitrary signals into SONET A synchronizer/de-synchronizer maps continuous format signals of an arbitrary rate into frames of pre-selected single common rate, such as SONET frames, with no bits changed and very little jitter or wander added. In this way, the continuous format signal may be car... | 02/21/2006 |
| 6956875 | Technique for communicating variable bit rate data over a constant bit rate link Variable bit rate information is transmitted across a transmission link (20) at a constant bit rate by multiplexing individual variable bit rate elementary data streams (161 and 162) into a composite data stream (18)... | 10/18/2005 |
| 6847659 | Methods and apparatus for reconfiguring protocol data when reducing multiplexed data streams The present invention provides methods and apparatus for reconfiguring protocol data for a multiplexed data stream which is reduced to carry fewer services for cable-side transmission in a cable television plant or the like. More particularly, the present invention ... | 01/25/2005 |
| 6292875 | Control device for storage device and method of accessing the storage device In a control device for a storage device in which data streams are respectively divided into unit data, which are distributed to storage parts and are sequentially read therefrom for every unit data, there is provided a buffer memory which stores data to ... | 09/18/2001 |
| 6198754 | Network system, transmitting device and receiving device A transmitting device cyclically distributes a plurality of cells to a plurality of lines in a predetermined order. The transmitting unit loads the same cell block number into the cells to be distributed to the lines in the same cycle, and transmits the c... | 03/06/2001 |
| 6101198 | Processor-based voice and data time slot interchange system A technique for performing a time slot interchange in a processor. The TSI process is surrounded by a multiplexing/demultiplexing circuit for converting a plurality of PCM highways into a single input serial data stream. The mux/demux circuit includes ela... | 08/08/2000 |
| 6061405 | Time domain source matched multicarrier quadrature amplitude modulation (QAM) method and apparatus A multicarrier transmission system (100) routes data symbols from a data source (142) to a multicarrier modulator (145). Each modulator (201, 202, 203) within the multicarrier modulator (145) is coupled to a corresponding gain adjuster (211, 212, 213) tha... | 05/09/2000 |
| 5878039 | Bus rate adaptation and time slot assignment circuit for a sonet multiplex system An interface device is provided which may be used to perform rate adaptation and time slot assignment, in either the transmit or receive directions, in a multiplexing unit for interfacing a high rate optical carrier line to a plurality of lower rate infor... | 03/02/1999 |
| 5737370 | Method for initializing a network A method for initializing a network for data transmission between a plurality of subscribers being connected to one another in ring-like fashion, includes sending a clock signal through the network in a continuous data stream, originating at a network pos... | 04/07/1998 |
| 5719747 | Interface unit for communication device with parts positioned on a printed-wiring board for achieving desirable operating characteristics An interface unit having a digital hierarchy interface function for a communication device has parts disposed on a printed-wiring board in a Layout to maintain desired interface unit characteristics. The interface unit includes a plurality of parallel B/U... | 02/17/1998 |
| 5719874 | Time-division-multiplexing method and apparatus In known optical distribution systems, a signal intended for the subscribers is distributed from a transmitting point to all network terminations (point-to-multipoint transmission). The receivers, which are connected to a passive optical network, are adap... | 02/17/1998 |
| 5712580 | Linear phase detector for half-speed quadrature clocking architecture A linear phase detector used with half-speed quadrature clock architecture is provided. The linear phase detector includes a first circuit receiving a data signal, a first half-speed quadrature clock signal and a second half-speed quadrature clock signal.... | 01/27/1998 |
| 5325354 | Synchronous terminal station receiving system Pointer information that shows the bit time slot in a frame of low order group signals in which a leading location of substantial data of the low order group signals is placed, is utilised to provide a synchronous terminal station system of a 1:N redundan... | 06/28/1994 |
| 5301196 | Half-speed clock recovery and demultiplexer circuit A clock recovery circuit and demultiplexer circuit which operate at half the data rate of a received data stream. The half-speed clock recovery circuit generates a 0 and 90-degree clock at half the rate of the incoming data. These clocks are sampled by a ... | 04/05/1994 |
| 5265095 | Method for inputting signals into and outputting signals out from subareas of the auxiliary signals of transport modules of a synchronous digital signal hierarchy Method for inputting signals into and outputting signals out of subareas of the auxiliary signals of transport modules of a synchronous digital signal hierarchy. The invention is based on the object of specifying a method for outputting signals from at le... | 11/23/1993 |
| 5251210 | Method and apparatus for transforming low bandwidth telecommunications channels into a high bandwidth telecommunication channel Low bandwidth telecommunications channels are transformed into a high bandwidth telecommunications channel by determining the relative transmission delays among a plurality of relatively low bandwidth channels which are to be combined into a relatively hi... | 10/05/1993 |
| 5128940 | Demultiplexer A demultiplexer has a main circuit section obtained by connecting a plurality of 1:2 demultiplexers, each for distributing a time-divisionally multiplexed signal into tow parts, to form a tree-like arrangement, and a clock frequency divider for frequency-... | 07/07/1992 |
| 5081619 | Digital signal multiplex communication system having signal path monitoring function The present invention relates to a digital signal multiplex and communication system having monitoring function of the signal path. The digital path monitoring method according to the present invention comprises step of counting "1"s included in informati... | 01/14/1992 |
| 5067126 | Method and apparatus for mapping a digital signal carrier to another A DS-3 to 28 VT1.5 SONET Interface Circuit is shown, without using standard intermediate DS-2 and DS-1 Desynchronizer Phase-Lock Loops. The elimination of DS-2 and DS-1 Desynchronizer Phase Lock Loops results in a significant reduction in cost and complex... | 11/19/1991 |
| 5014272 | Frame synchronizer for detecting misframes with different shift patterns A frame synchronizer is adapted to receive an incoming high-speed TDM (time division multiplex) signal of a framed structure containing, at frame intervals, a sequence of identical synchronization bit patterns and a sequence of byte-length data signals. A... | 05/07/1991 |
| 4993013 | Monitor system for multiplex equipment A monitor system for a multiplex equipment, comprising a multiplexing unit for multiplexing low speed group input signals of plural channels into a high speed group output signal and a demultiplexing unit for demultiplexing a high speed group input signal... | 02/12/1991 |
| 4920535 | Demultiplexer system A demultiplexing circuit includes a frame synchronization circuit which simultaneously detects the occurrence of a predetermined frame synchronization pattern and the occurrence of a predetermined identification byte within the frame synchronization patte... | 04/24/1990 |
| 4866711 | Method of multiplex/demultiplex processing of information and equipment for performing the method An information processing system includes a transmitter, which converts parallel information to serial, and a receiver, which receives the serial information and reconverts the same to parallel for use by a further processing unit. Structure is provided t... | 09/12/1989 |
| 4791628 | High-speed demultiplexer circuit A demultiplexer for demultiplexing a multiplexed input data signal into M output channels using M sequencer means clocked from an overlapping M phase system clock. The system clock operates at a frequency equal to the input data signal rate divided by M. ... | 12/13/1988 |
| 4697262 | Digital carrier channel bus interface module for a multiplexer having a cross-connect bus system A digital carrier channel bus interface module is disclosed for a multiplexer having a cross-connect bus system. Random access memory is loaded or unloaded by a serial-to-parallel or parallel-to-serial converter respectively with data in parallel format o... | 09/29/1987 |
| 4602367 | Method and apparatus for framing and demultiplexing multiplexed digital data If each data channel comprising a set of multiplexed data channels contains channel identity information, a single framing detector operating on one channel can provide a framing detection operation regardless of where the search is commenced thereby avoi... | 07/22/1986 |
| 4535451 | Fourth-order digital multiplex system for transmitting a plurality of digital signals at a nominal bit rate of 44 736 kbit/s The CCITT has given recommendations for two types of hierarchies of PCM multiplex systems for telephony transmission: a first type based on a first-order PCM multiplex system having a nominal bit rate of 2048 kbit/s for 30 telephone channels while employi... | 08/13/1985 |
| 4387459 | Non-buffered loop-timed channel bank In a digital transmission system, a loop-timing technique is provided for a channel bank which demultiplexes a high speed data stream into a plurality of lower rate channels, and which multiplexes a plurality of lower rate channels to a high speed data st... | 06/07/1983 |
