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| Number | Title | Issue Date |
| 7940808 | Communications system with symmetrical interfaces and associated methods A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is... | 05/10/2011 |
| 7920601 | Vehicular communications system having improved serial communication A communications system for controlling equipment associated with a vehicle, includes a micro-controller (604) and a digital serial communication link (621, 622, 662, 663) using a multiplexed timing signal and first data signal. A camera or image senso... | 04/05/2011 |
| 7907640 | Synchronizing clocks across a communication link A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave cl... | 03/15/2011 |
| 7876792 | Network element clocking accuracy and stability monitoring over a packet-switched network Various exemplary embodiments include a method and related system and monitoring entity including one or more of the following: generating timing information at a master node in a packet-switched network, the timing information specifying a value of a master clock; ... | 01/25/2011 |
| 7792158 | Media streaming synchronization A system and method for closely synchronizing the transmission of real-time data streams is described. Synchronization data is transmitted by a cycle master for receipt by one or more cycle slaves. A cycle slave updates an internal state based on synchronization dat... | 09/07/2010 |
| 7729387 | Methods and apparatus for controlling latency variation in a packet transfer network Methods and apparatus for controlling latency variation of packets received in a packet transfer network are provided. A plurality of packets is received at a network element of a receive node of the packet transfer network. A time-stamp is provided for each of the ... | 06/01/2010 |
| 7715445 | System and method for minimizing transmit latency uncertainty in 100 Mb RMII ethernet physical layer devices A system and method for minimizing transmit latency uncertainty in a 100 Mb RMII Ethernet physical layer device is disclosed. A 100 Mb RMII Ethernet transmit physical layer device comprises a divide circuit that selects a phase of a transmit clock signal for transmi... | 05/11/2010 |
| 7486703 | Communications system with symmetrical interfaces and associated methods A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is... | 02/03/2009 |
| 7486702 | DDR interface for reducing SSO/SSI noise An improved DDR interface uses single-ended technology and phase-shifts all output data signals and the output source clock signal so that each output signal switches at a different time so that IDDQ spikes caused by I/O switching do not accumulate. A dynamic phase ... | 02/03/2009 |
| 7466724 | Apparatus and method of analyzing packetized data spanning over multiple clock cycles A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the pac... | 12/16/2008 |
| 7362778 | Plesiochronous demultiplexer A desynchronizer for extracting and desynchronizing a tributary signal from a multiplex signal at its original data rate has a buffer memory for temporarily storing tributary data bits extracted from the multiplex signal, an adjustable oscillator for generating a re... | 04/22/2008 |
| 7362771 | Reduced latency FIFO A First-In-First-Out (FIFO) block to buffer a packet having a size is presented. The FIFO block includes a receiver to receive a data frame including the packet and overhead information, and to extract the packet from the data frame. A buffer has a plurality of memo... | 04/22/2008 |
| 7353446 | Cyclic redundancy check circuit for use with self-synchronous scramblers The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. ... | 04/01/2008 |
| 7352689 | Method for optimizing phase factor of sub-block signal in partial transmit sequence orthogonal frequency division multiplexing system A method for optimizing phase factors in partial transmit sequence orthogonal frequency division multiplexing system. The method includes initializing sub-block signals by applying an initial phase factor to the sub-block signals in all sub-blocks; setting a referen... | 04/01/2008 |
| 7352737 | Communications in an asynchronous cellular wireless network Systems and techniques are disclosed for establishing a reference corresponding to the timing of a received signal from the first source, determining the timing for each received signal from a plurality of second sources, adjusting the reference to the timing of the... | 04/01/2008 |
| 7348821 | Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable... | 03/25/2008 |
| 7333517 | Method and system for accurately calculating latency variation on an end-to-end path in a network A high-resolution, per-packet measurement tool for analyzing a computer network that operates by sending a predetermined number of packets from a sender machine to a receiver machine with measurement information inserted into the packet. The system kernel at the sen... | 02/19/2008 |
| 7295845 | Method and node for the set-up of a connection in a telecommunication network In a method for the set-up of a connection in a communication network, the set-up is initiated with an initial message (12) from an originating control node (ON) to a terminating control node (TN) of the connection and the establishment of a bearer for the co... | 11/13/2007 |
| 7292606 | Two-stage symbol alignment method for ADSL transmission in the presence of TCM-ISDN interferers Method embodiments for achieving hyperframe symbol synchronization are disclosed, along with device and system embodiments for implementing such methods. In one embodiment, the method comprises: receiving a pilot signal having at least two phase states; measuring th... | 11/06/2007 |
| 7289543 | System and method for testing the operation of a DLL-based interface A high-speed bit stream data conversion circuit receives a first bit stream(s) and recovers a clock signal from the first bit stream(s). The data conversion circuit then produces a second bit stream(s) having a second lower bit rate. A control loop adjusts the phase... | 10/30/2007 |
| 7289538 | Clock reconstruction for time division multiplexed traffic transported over asynchronous ethernet networks A clock reconstruction mechanism for synchronous TDM communications traffic transported over asynchronous networks such as Ethernet networks. The invention is applicable to edge switches in Metropolitan Area Networks (MANs) that transport legacy TDM traffic using a ... | 10/30/2007 |
| 7286569 | Full-rate clock data retiming in time division multiplexers Apparatus for use in providing full-rate clock data retiming in a time division multiplexer, wherein the time division multiplexer includes an N to 1 time division multiplexer circuit and a retiming circuit, comprises the following circuitry. The apparatus comprises... | 10/23/2007 |
| 7280629 | Method and apparatus for receiving data based on tracking zero crossings Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adop... | 10/09/2007 |
| 7274705 | Method and apparatus for reducing clock speed and power consumption A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the ... | 09/25/2007 |
| 7269421 | Control of frame timing on handover The uplink transmission timing from a mobile communications device is defined with reference to the downlink reception timing of signals from a particular reference cell. When that reference cell is removed from the active set, there is defined a virtual reference c... | 09/11/2007 |
| 7266624 | Programmable layered sub-system interface A programmable layered sub-system interface includes an extension sub-layer module, a physical coding sub-layer module, a physical media attachment module, an input module, an output module, a 1st switch module and a 2nd switch module. The 1 | 09/04/2007 |
| 7263117 | Dual control analog delay element and related delay method A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setti... | 08/28/2007 |
| 7257129 | Memory architecture with multiple serial communications ports A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area netwo... | 08/14/2007 |
| 7253671 | Apparatus and method for compensating for clock drift in downhole drilling components A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded num... | 08/07/2007 |
| 7239651 | Desynchronizer having ram based shared digital phase locked loops and sonet high density demapper incorporating same A SONET demapper includes three desynchronizers, each of which includes a RAM-based, shared digital phase locked loop, shared elastic storage, and twenty-eight divide-by 33/34/44/45 counters. Unlike a conventional desynchronizer which uses separate FIFOs for each of... | 07/03/2007 |
| 7234099 | High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurali... | 06/19/2007 |
| 7227876 | FIFO buffer depth estimation for asynchronous gapped payloads A desired FIFO buffer fill level is continuously derived during mapping or demapping of plesiosynchronous data signals into synchronized data signals, or vice-versa. One of j predefined integer values Ii is repetitively consecutively produced during each ... | 06/05/2007 |
| 7209492 | DSO timing source transient compensation System and method for compensating for DS0 timing source transients, such as may occur during a switchover to a new external reference, is described. In one embodiment, an SFI control signal is monitored for embedded frame position information. When the frame positi... | 04/24/2007 |
| 7202575 | Semiconductor integrated circuit device There is disclosed a semiconductor integrated circuit device capable of eliminating an influence of a power voltage drop generated in a circuit disposed in the semiconductor integrated circuit device to inhibit an operation defect or an operation speed decrease of t... | 04/10/2007 |
| 7200143 | Intergrated services digital network private branch exchange capable of choosing synchronization clock source automatically An integrated services digital network private branch exchange, which is capable of automatically choosing a synchronization clock source. The integrated services digital network private branch exchange comprises a plurality of trunk chips, a plurality of subscribe ... | 04/03/2007 |
| 7197102 | Method and apparatus for clock-and-data recovery using a secondary delay-locked loop A clock and data recovery circuit includes a delay-locked-loop adapted to recover data from a data stream: and a phase-locked-loop in communication with the delay-locked-loop and adapted to recover a clock signal from the data stream. ... | 03/27/2007 |
| 7193429 | Serial data communication system having plurality of data transmission paths Data is serially transferred from an IC1 to an IC2 through a plurality of data transmission paths. Elastic buffers are connected to the plurality of signal paths corresponding the plurality of data transmission paths. A skew adjustment circuit cancels ... | 03/20/2007 |
| 7190906 | Linear full-rate phase detector and clock and data recovery circuit Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate and receiving a clock signal having a first clock frequency, and alternating between a first level and a ... | 03/13/2007 |
| 7190709 | Early-late correlation for timing error correction in data communication receivers A timing error correction technique for use in data communications receivers such as WLAN (Wireless Local Area Network) receivers is provided where an input signal is received that has a timing error, the timing error is corrected, and a signal having a corrected ti... | 03/13/2007 |
| 7167534 | Oversampling clock recovery circuit applicable not only to high rate data but also to low rate data In an oversampling clock recovery circuit comprising first through fourth phase comparators (PD1 to PD4) and a majority circuit (10), DOWN signal output terminals (DN2(out), DN3(out)) of the second and the third phase comparators a... | 01/23/2007 |
