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| Number | Title | Issue Date |
| 8121139 | Communication module and communication apparatus A communication module mounted on a communication apparatus which includes plural communication modules, plural apparatus side signal processing circuits for processing a communication signal which is transmitted to and received from the communication modules by a p... | 02/21/2012 |
| 7986707 | Method and system for rules based workflow of media services A method for executing services over an enterprise service bus includes analyzing a message of a first service to a second service to determine a nature of a digital media object sent from the first service to the second service, analyzing one or more media rules to... | 07/26/2011 |
| 7899071 | Serial bus structure Embodiments of the invention relate to a bus structure for a serial bus for communicatively coupling a plurality of nodes. Each node is coupled to the transmit channel via a logic gate. The transmit channel is looped back as a receive channel to the receive terminal... | 03/01/2011 |
| 7830906 | Variable time division multiplex transmission system A time division multiplex transmission system transmits information on multiple channels by using a transmission path with variable time division multiplexing. The variable time division multiplex transmission system of this invention is equipped with multiple chann... | 11/09/2010 |
| 7778267 | Bus system A bus system for providing a common data transmission path for N data sources that have M data bits. The N data sources are connected to M interconnections correspondingly through N bus cells each of which includes logic circuits for selectively providing the data b... | 08/17/2010 |
| 7751418 | Apparatus and method for controlling data transmission An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control... | 07/06/2010 |
| 7724762 | Efficient transmission of packets within a network communication device Systems and methods for efficient transmission of packets within a network communication device are described herein. Some illustrative embodiments include a network communication device that includes a plurality of ports (each port configured to communicate with on... | 05/25/2010 |
| 7532636 | High bus bandwidth transfer using split data bus Methods and apparatus for achieving high bus bandwidth transfer using a split data bus. A data bus is split into multiple segments whose access is, individually controlled by an arbitration control unit in a manner that supports concurrent data transfers. Thus, the ... | 05/12/2009 |
| 7440447 | Techniques for path finding and terrain analysis A system for path finding and terrain analysis. The system includes at least one processing unit, a graph processing unit and an artificial intelligence logic unit. A local bus is coupled to the at least one processing unit, the graph processing unit, the artificial... | 10/21/2008 |
| 7426216 | Advanced telecommunications router and crossbar switch controller The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. It also includes a matrix circuit coupled to the input term... | 09/16/2008 |
| 7424028 | Cable modem for connecting customer premises equipment and method of controlling flow of data between cable modem and customer premises equipment A cable modem for connecting Customer Premises Equipment (CPE) includes a Media Access Control (MAC) layer controller, a Logical Link Control (LLC) bridge (113) interacting with the MAC layer controller, an IP stack processing IP frames and interacting with t... | 09/09/2008 |
| 7415006 | Method and system for transporting data packets of a data stream For transporting data packets of a data stream between a packet-oriented network (LAN) and a channel-oriented data stream processing module (VMOD), a data stream controller (ST) is provided which, via a data channel allocation module (VMUX), accesses an interface mo... | 08/19/2008 |
| 7411972 | Link layer device with non-linear polling of multiple physical layer device ports In a communication system comprising a link layer device connectable to one or more physical layer devices, at least a given one of a plurality of ports of the one or more physical layer devices is designated as a port for which status information is to be requested... | 08/12/2008 |
| 7373425 | High-speed MAC address search engine Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary... | 05/13/2008 |
| 7369550 | Method and apparatus for locking a table in a network switch An apparatus and method are disclosed for locking a table within a network switch. The table is used to store entries that contain addresses of network stations connected to the network switch. A scheduler regulates access to the address table by allocating prescrib... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7359384 | Scheduling of guaranteed-bandwidth low-jitter traffic in input-buffered switches A switch schedules guaranteed-bandwidth, low-jitter-traffic characterized by a guaranteed rate table (GRT) method. A rate matrix generated from collected provisioning information is decomposed into schedule tables by a low jitter (LJ) decomposition method. The LJ de... | 04/15/2008 |
| 7360007 | System including a segmentable, shared bus A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adap... | 04/15/2008 |
| 7352746 | Frame forwarding installation A frame forwarding installation on the side of a transmitting terminal refers to a header of a received frame and determines whether a host application is a real-time application. If the application is a real-time application, the received frame is sent to a plurali... | 04/01/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7339943 | Apparatus and method for queuing flow management between input, intermediate and output queues An apparatus is described that includes a plurality of queuing paths. Each of the queuing paths further comprises an input queue, an intermediate queue and an output queue. The input queue has an output coupled to an input of the intermediate queue and the input of ... | 03/04/2008 |
| 7330992 | System and method for read synchronization of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 02/12/2008 |
| 7324464 | Communication system with connectable interface device The communication system includes multiple participating devices connected with each other by a data line. At least one connection device for connection to a corresponding participant device defined as associated with it is connected to the data line. The communicat... | 01/29/2008 |
| 7324537 | Switching device with asymmetric port speeds In general, in one aspect, the disclosure describes a switching device that includes a plurality of ports. The ports operate at asymmetric speeds. The apparatus also includes a switching matrix to provide selective connectivity between the ports. The apparatus furth... | 01/29/2008 |
| 7313693 | Secure transmission using adaptive transformation and plural channels A method, apparatus and computer program product for transmitting data secures the data by adaptively transforming it and spreading the transformed data piecewise over plural transmission channels. The method, apparatus and computer program product may select low-co... | 12/25/2007 |
| 7313146 | Transparent data format within host device supporting differing transaction types A system for servicing packet data transactions and input/output transactions includes an input port, an output port, a node controller, a packet manager, and a switching module. The input port is receives communications from a communicatively coupled processing dev... | 12/25/2007 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
| 7289347 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 10/30/2007 |
| 7282947 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 10/16/2007 |
| 7278060 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 10/02/2007 |
| 7274689 | Packet switch with one-stop buffer in memory with massive parallel access A broadband packet switch that handles all packets that arrive within the same frame time by simultaneously bit-pipelining the packets into different sections of the one-stop packet buffer through an input switch. Each packet remains in is selected section until its... | 09/25/2007 |
| 7272151 | Centralized switching fabric scheduler supporting simultaneous updates A system for servicing data transactions within a processing device using common data paths. The system is broadly comprised of: a plurality of source agents operable to transmit a plurality of data cells; a plurality of destination agents operable to of data cells;... | 09/18/2007 |
| 7272672 | High speed bus with flow control and extended burst enhancements between sender and receiver wherein counter is maintained at sender for free buffer space available In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of flow control and extended burst transfers are described. ... | 09/18/2007 |
| 7272682 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 09/18/2007 |
| 7266633 | System and method for communicating the synchronization status of memory modules during initialization of the memory modules A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during in... | 09/04/2007 |
| 7263587 | Unified memory controller A unified memory controller (UMC) is disclosed. The UMC may be used in a digital television (DTV) receiver. The UMC allows the DTV receiver to use a unified memory. The UMC accepts memory requests from various clients, and determines which requests should receive pr... | 08/28/2007 |
| 7260685 | Memory hub and access method having internal prefetch buffers A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history lo... | 08/21/2007 |
