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| Number | Title | Issue Date |
| 8085789 | Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechani... | 12/27/2011 |
| 7522611 | Variable sized information frame switch for on-board security networks This switch comprises a central buffer memory (30) for temporarily storing the data traffic which it receives, the time for performing the routings and for carrying out the resendings of the messages that it receives. It is noteworthy in that its central buff... | 04/21/2009 |
| 7486683 | Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adap... | 02/03/2009 |
| 7423969 | Process for storing transmission units and a network communications device The present invention relates to a process for storing transmission units in interworking between networks of differing protocol structure, in particular between ATM networks and Ethernet networks, and a corresponding network communications device. In accordance wit... | 09/09/2008 |
| 7420977 | Method and apparatus of inter-chip bus shared by message passing and memory access A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/com... | 09/02/2008 |
| 7417993 | Apparatus and method for high-throughput asynchronous communication One embodiment of the present invention provides a system for high-throughput asynchronous communication that includes a sender and a receiver. A sender's first-in, first-out (FIFO) buffer is coupled to an input of the sender, a receiver's FIFO buffer is coupled to ... | 08/26/2008 |
| 7411968 | Two-dimensional queuing/de-queuing methods and systems for implementing the same Systems and methods for queuing and de-queuing packets in a two-dimensional link list data structure. A network processor processes data for transmission for a plurality of Virtual Connections (VCs). The processor creates a two-dimensional link list data structure f... | 08/12/2008 |
| 7398326 | Methods for management of mixed protocol storage area networks The invention provides improvements on a digital data processing system of the type having a first set of hosts, storage devices or other components coupled for communication with a first network manager. A second set of components is likewise coupled to a second ne... | 07/08/2008 |
| 7370197 | Method and system for authenticating messages A method and system for authenticating a message is described, in which the message contains a network address, at least a portion of which is a digital fingerprint. Embedded in the message is data, such as a code, that indicates the size of the digital fingerprint.... | 05/06/2008 |
| 7352751 | Accounting for link utilization in scheduling and billing An apparatus for transferring data in a telecommunications network. The apparatus includes a memory in which a packet memory length is stored. The apparatus includes a mechanism for determining a link length for the packet that will be sent into the network based on... | 04/01/2008 |
| 7348820 | Method and apparatus for glitch-free control of a delay-locked loop in a network device A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals i... | 03/25/2008 |
| 7343413 | Method and system for optimizing a network by independently scaling control segments and data flow A server array controller that includes a Data Flow Segment (DFS) and at least one Control Segment (CS). The DFS includes the hardware-optimized portion of the controller, while the CS includes the software-optimized portions. The DFS performs most of the repetitive... | 03/11/2008 |
| 7336612 | Switching system for telecommunication networks The present invention is directed to a high performance broadband ATM switching system comprised of concentrator, non-recirculating sort-trap and queuing stages. The concentrator stage concentrates cells entering the switch by discarding idle inputs thereto. Cells a... | 02/26/2008 |
| 7330480 | Adaptive network resource control An admissions control technique improves processing capacity utilization in a token-based admission control scheme by matching token allocation to actual processing requirements. In an exemplary application, the processing capacity of a processing entity is discrete... | 02/12/2008 |
| 7295560 | Method and apparatus of inter-chip bus shared by message passing and memory access A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/com... | 11/13/2007 |
| 7292570 | Self-routing device for switching packets of different lengths A technique for accommodating packets of different lengths at minimal cost to hardware complexity with a self-routing switch primitive with an associated switching mechanism that accommodates packets of different lengths encapsulated in a new packet format. The swit... | 11/06/2007 |
| 7269168 | Host bus adaptor-based virtualization switch Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a se... | 09/11/2007 |
| 7249220 | Storage system To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data caching control units are connected to each other through an interconnectio... | 07/24/2007 |
| 7249228 | Reducing the number of block masks required for programming multiple access control list in an associative memory Mechanisms for reducing the number of block masks required for programming multiple access control lists in an associative memory are disclosed. A combined ordering of masks corresponding to multiple access control lists (ACLs) is typically identified, with the mult... | 07/24/2007 |
| 7239645 | Method and apparatus for managing payload buffer segments in a networking device A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the d... | 07/03/2007 |
| 7236488 | Intelligent routing switching system An intelligent routing and switching system includes an interface for coupling said system to an external network and a switch fabric for selectively routing bits of data being exchanged with an external network through the interface. The switch fabric includes an a... | 06/26/2007 |
| 7224693 | Long packet handling A switch for switching packets from a plurality of sources. The switch includes a memory in which portions of packets are stored. The switch includes a transferring mechanism which transfers predetermined portions of a packet to the memory as the predetermined porti... | 05/29/2007 |
| 7203193 | In-band message synchronization for distributed shared memory packet switch The present invention is directed to synchronizing notification messages transmitted to egress control units to allow an even distribution of the messages. A plurality of packet buffer units (PBUs) may concurrently transmit notification messages to a particular egre... | 04/10/2007 |
| 7191366 | Method and intelligent slave device transfer control unit for implementing seamless error resumption in a shared memory bus structure A method and apparatus are provided for implementing seamless error resumption in a shared memory bus structure. Controls and data are stored for each read operation and each write operation. Each read operation and each write operation is monitored to determine whe... | 03/13/2007 |
| 7187685 | Multi-module switching system A multi-module switching system comprising at least two switching modules adapted for receiving data packets from at least one input adapter and transmitting the data packets to at least one output adapter, each of the switching modules including a shared buffer for... | 03/06/2007 |
| 7177973 | Method and apparatus for extending communications over a universal serial bus through domain transformation Methods and apparatuses are described for improving information transfer over a universal serial bus (USB). In some embodiments, an apparatus includes a USB-compliant near-end link and control logic coupled with the USB-compliant near-end link. The control logic may... | 02/13/2007 |
| 7174394 | Multi processor enqueue packet circuit The present invention provides a system and method for a plurality of independent processors to simultaneously assemble requests in a context memory coupled to a coprocessor. A write manager coupled to the context memory organizes segments received from multiple pro... | 02/06/2007 |
| 7142538 | Message-based communication over bus between cards in an electronic module A method for communicating between cards in an electronic module is provided. The method includes generating a message for transmission at a first card. The message is transmitted over a bus to a second card by-passing an IP stack at the first card. A queue at the s... | 11/28/2006 |
| 7132866 | Method and apparatus for glitch-free control of a delay-locked loop in a network device A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals i... | 11/07/2006 |
| 7131001 | Apparatus and method for secure filed upgradability with hard wired public key An apparatus and for enabling functionality of a component, wherein the apparatus includes an identification module having an identification number stored therein, and a hash function module in communication with the identification module. A host is provided and is ... | 10/31/2006 |
| 7120739 | Storage system To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units (10) and data caching control units (21) are connected to each other t... | 10/10/2006 |
| 7120117 | Starvation free flow control in a shared memory switching device A shared memory packet switching device includes: a shared memory providing a shared memory space; an input logic unit associated with at least one receive port, and being operative to determine whether the associated receive port is saturated by determining whether... | 10/10/2006 |
| 7110409 | Internal ATM-based multi-terminal client installation and method of operating same A broadcaster broadcasts all network cells received via a receive channel of a telecommunication line serving the installation to digital loops including terminals. A collector collects ATM cells produced by the terminals and transmits them in an emit channel of the... | 09/19/2006 |
| 7111123 | Circuit and method to allow searching beyond a designated address of a content addressable memory A content addressable memory includes a priority encoder that is in communication with an array of the content addressable memory cells to receive match signals, and from the match signals generating an output index signal in accordance with a priority sequence of t... | 09/19/2006 |
| 7103059 | Scalable 2-stage interconnections Modifications to the 2-stage interconnection to allow flexible scalability. Different switching fabrics having a range of different sizes can be constructed out of the same set of I/O switching nodes through this modified 2-statge interconnection, which can further ... | 09/05/2006 |
| 7103039 | Hardware load balancing through multiple fabrics The present invention relates to a method and apparatus for balancing loads in multiple switching fabrics. Each switching fabric comprises data ports through which data frames enter or exit the switching fabric. In one embodiment, the apparatus includes a buffer and... | 09/05/2006 |
| 7103053 | Gigabit switch on chip architecture A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A ... | 09/05/2006 |
| 7099345 | Method and system for buffering a data packet for transmission to a network Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag use... | 08/29/2006 |
| 7099335 | Communication control apparatus A communication control apparatus which effectively uses a memory and does not need complicated hardware is realized. Each area of a frame assembly memory 2 is set to the maximum frame length which is handled. When a cell of a new connection is inputted, a me... | 08/29/2006 |
| 7075938 | Common buffer memory control apparatus A common buffer memory control apparatus controls a common buffer memory which is used to store message data items each of which is divided into a plurality of cells based on an asynchronous transfer mode. The common buffer memory control apparatus includes a free b... | 07/11/2006 |
