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| Number | Title | Issue Date |
| 8018926 | Differential delay compensation In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address... | 09/13/2011 |
| 7773591 | Integrated memory for storing egressing packet data, replay data and to-be egressed data An integrated egress/replay memory structure is provided with split rate write and read ports and means for managing at least three types of data moving into, through and/or out of the integrated memory structure, namely: (1) currently egressing packet data; (2) rep... | 08/10/2010 |
| 7773590 | Combined interface and non-interface specific associative memory lookup operations for processing of packets Mechanisms for programming and performing combined interface and non-interface specific associative memory lookup operations for processing of packets are disclosed. One system includes multiple interfaces, a content-addressable memory, multiple memory entries and a... | 08/10/2010 |
| 7596134 | Flexible method and apparatus for performing digital modulation and demodulation A method of processing data based on programmed instructions includes referencing a number of locations in memory by forming addresses and correct buffer mappings corresponding to separate buffers in the plurality of buffers, and communicating data from the referenc... | 09/29/2009 |
| 7457286 | Accelerating the shortest path problem The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a grou... | 11/25/2008 |
| 7359360 | Communication system supporting wireless communication of packet data and method and arrangement relating thereto A communication system supporting communication of packet data. It comprises a core network, which includes a number of packet data support nodes, a number of gateway nodes for communication with external packet data networks, and a number of radio networks. Each ra... | 04/15/2008 |
| 7286498 | Validation method and data structures for wireless communications A response monitoring apparatus using a remote including an electrical circuit including a user activated input, a transmitter, and a receiver, where the electrical circuit is adapted to detect operation of the user activated input and temporarily activates the rece... | 10/23/2007 |
| 7283528 | On the fly header checksum processing using dedicated logic A packet header processing engine includes a packet processing unit that is configured to generate the packet header information based on the packet header data. A checksum generating unit is connected to the packet processing unit. The checksum generating unit is c... | 10/16/2007 |
| 7277427 | Spatially distributed routing switch A router has N1 local signal input terminals for connection to respective local signal sources for supplying respective local input signals, a local output interface including M1 local signal output terminals, and an input expansion terminal. A signal received at an... | 10/02/2007 |
| 7266128 | Time-slot interchange switches having efficient block programming and on-chip bypass capabilities and methods of operating same Time-slot interchange (TSI) switches include a data memory having first entries therein that contain serial data received by the switch and a connection memory having second entries therein. When programmed, these second entries contain addresses of a plurality of t... | 09/04/2007 |
| 7263593 | Virtualization controller and data transfer control method Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a virtualization controller for controlling data transfer between a host sys... | 08/28/2007 |
| 7263101 | Host digital terminal A host digital terminal HDT performs backbone functions to a subscriber access network, while the network side of the HDT is connected to many data transfer networks and the other side of the HDT is connected to many optical network units ONUs. The HDT performs mutu... | 08/28/2007 |
| 7260518 | Network flow switching and flow data report The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a netwo... | 08/21/2007 |
| 7243183 | SONET data byte switch A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices is disclosed. The memory devices include a first memory bank configur... | 07/10/2007 |
| 7239630 | Dedicated processing resources for packet header generation A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit may include a single execution sect... | 07/03/2007 |
| 7236501 | Systems and methods for handling packet fragmentation A packet header processing engine receives a header of a packet. The received header includes a size of the packet. A maximum transfer unit size of a destination interface of the packet may be determined. The packet header processing engine determines whether the si... | 06/26/2007 |
| 7236497 | Facilitating arbitration via information associated with groups of requesters According to some embodiments, a requester is selected in accordance with information associated with a first and second groups of requesters. For example, a first input may receive a first priority signal, indicating whether at least one of a first group of request... | 06/26/2007 |
| 7215662 | Logical separation and accessing of descriptor memories A packet header processing engine includes a memory having a number of distinct portions for respectively storing different types of descriptor information for a header of a packet. A packet header processing unit includes a number of pointers corresponding to the n... | 05/08/2007 |
| 7212530 | Optimized buffer loading for packet header processing A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a f... | 05/01/2007 |
| 7200151 | Apparatus and method for arbitrating among equal priority requests A switch for use with an InfiniBand network having a management port adapted to arbitrate among equal priority signals requesting attention from ports on the switch. In particular, the management port included three registers that are used to arbitrate between the r... | 04/03/2007 |
| 7187673 | Technique for creating a machine to route non-packetized digital signals using distributed RAM A signal router routes N inputs to M outputs. All inputs signals are ultimately applied to a data buss by spreading across multiple buss lines and time multiplexing. The data are read from the buss and written in identical images to K random access memories. The mem... | 03/06/2007 |
| 7187676 | Apparatus and method for steering a communication to an open stream An apparatus and method for expeditiously steering a received communication (e.g., packet, cell, frame) to one or more communication streams. When a new communication stream is opened on a network interface circuit or other Primary Point of Attachment (PPA), the pro... | 03/06/2007 |
| 7180893 | Parallel layer 2 and layer 3 processing components in a network router A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a f... | 02/20/2007 |
| 7170885 | Packet switching method and apparatus thereof A packet switching is performed according to a routing information for relaying particular packets which is produced by the route computation based on the information of a received packet and the kept parts-of-routing-information useful as a basis for the route comp... | 01/30/2007 |
| 7170902 | Cross-bar switch incorporating a sink port with retry capability A cross-bar switch includes a set of input ports to accept data packets and a set of sink ports in communication with the input ports to forward the data packets. Each sink port includes a communications link interface with a Retry input. When a signal is asserted o... | 01/30/2007 |
| 7158520 | Mailbox registers for synchronizing header processing execution A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. Mailbox registers allow the L2 and L3 header generation un... | 01/02/2007 |
| 7149213 | Wireless computer system with queue and scheduler A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the ... | 12/12/2006 |
| 7142543 | High speed programmable counter A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the... | 11/28/2006 |
| 7126947 | Switch having external address resolution interface A network switch that has a plurality of input ports that receive data packets. An external interface is connected to the plurality of input ports. The external interface externally transmits the data packets for processing, and receives the data packets after proce... | 10/24/2006 |
| 7123585 | Cross-bar switch with bandwidth allocation Each sink port in a cross-bar switch provides for allocating bandwidth among data packets. Packets are assigned priority levels, and the cross-bar switch regulates bandwidth allocation for each priority level. A sink port records traffic volume for packet data of ea... | 10/17/2006 |
| 7120728 | Hardware-based translating virtualization switch Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a se... | 10/10/2006 |
| 7116672 | Method and apparatus for reducing flooding in bridged networks A method and apparatus for reducing flooding in a bridged network. The invention generally allows broadcast flooding for a predefined limited time period to permit mapping of a MAC address to a port by the bridge and disallows broadcast flooding for a second predefi... | 10/03/2006 |
| 7111054 | Customer premises equipment autoconfiguration A system and method for automatically configuring customer premises equipment, the system including a search module configured to select a set of configuration values and to create a discover packet including the set of configuration values. The discover packet is t... | 09/19/2006 |
| 7106730 | Method and apparatus for processing frame classification information between network processors A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-swit... | 09/12/2006 |
| 7107476 | Memory system using non-distributed command/address clock signals A memory system that includes a plurality of memory devices includes: a controller for outputting a first clock signal, a second signal and a plurality of command/address input signals corresponding to the plurality of memory devices, respectively; and a register an... | 09/12/2006 |
| 7085860 | Method and apparatus for a non-disruptive recovery of a single partition in a multipartitioned data processing system A method, apparatus and program product for the non-disruptive recovery of a single partition in a multipartitioned data processing system. A server contains multiple partitions connected to a single channel adapter which is used to send data and commands to a fabri... | 08/01/2006 |
| 7082139 | Cross-bar switch with sink port accepting multiple packets A cross-bar switch includes a set of input ports to receive data packets and a set of sink ports in communication with the input ports to receive the data packets and forward them onto a communications link. Each sink port is adapted to concurrently receive multiple... | 07/25/2006 |
| 7075557 | Method of and apparatus for handling high bandwidth on-screen-display graphics data over a distributed IEEE 1394 network utilizing an isochronous data transmission format On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display... | 07/11/2006 |
| 7068672 | Asynchronous receive and transmit packet crosspoint A packet crosspoint works with an arbiter to control the number of packets being received at the input ports of the cross-connect from traffic sources coupled thereto. This is accomplished by monitoring the number of packets waiting in buffers in the output ports, a... | 06/27/2006 |
| 7058073 | Arrangement and method for transmitting data over a TDM bus The invention relates to a TDM backplane bus system, in which a Frame Synchronisation signal is developed from an external communication signal, a data clock signal is produced from a free running clock oscillator independent of the FS signal, to select the frequenc... | 06/06/2006 |
