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| Number | Title | Issue Date |
| 8085764 | Egress selection switch architecture with power management A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents t... | 12/27/2011 |
| 7630363 | Apparatus for adjusting receiving time point of burst data in optical burst switching network and method thereof An apparatus and method for adjusting a receiving time point of burst data in an optical burst switching network is provided. The method includes comparing a reference time point of a node with a time slot boundary of the burst data; and adjusting the time slot boun... | 12/08/2009 |
| 7522587 | Flexible bandwidth allocation in high-capacity grooming switches A method and apparatus for flexible sharing of bandwidth in switches with input buffering by dividing time into a plurality of frames of time slots, wherein each frame has a specified integer value of time slots. Counters associated with the input-output queues of t... | 04/21/2009 |
| 7430202 | System and method of tributary time-space switching A tributary time-space switch and a method of switching are provided having low memory requirements. The switch includes a number of inputs and outputs. Each of the inputs receives an input data stream carrying tributary payloads from an external input link that are... | 09/30/2008 |
| 7417985 | Egress selection switch architecture with power management A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents t... | 08/26/2008 |
| 7360050 | Integrated circuit memory device having delayed write capability An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command s... | 04/15/2008 |
| 7356043 | Network channel access protocol—slot scheduling Network channel access protocol is disclosed. More particularly, a distributed, locally determined, channel access protocol that adapts to load, avoids interference and controls access by a group of nodes to a set of shared channels is disclosed. Shared channel spac... | 04/08/2008 |
| 7353288 | SONET/SDH payload re-mapping and cross-connect Multiple frames of SDH framed data are received. Each frame has an overhead portion and a payload portion. The payload portions of multiple frames are identified and extracted. These payloads are switched and re-mapped to a different STM structure as required. ... | 04/01/2008 |
| 7349387 | Digital cross-connect Two or more cross-connect ICs are interconnected. Each IC directly receives some, but not all, of the system inputs, and outputs to some, but not all, outputs. Each cross-connect IC has a switch matrix that has the same number of inputs as the system, and a lesser n... | 03/25/2008 |
| 7339947 | Network channel access protocol—frame execution Network channel access protocol is disclosed. More particularly, a distributed, locally determined, channel access protocol that adapts to load, avoids interference and controls access by a group of nodes to a set of shared channels is disclosed. Shared channel spac... | 03/04/2008 |
| 7339926 | System and method for wireless communication in a frequency division duplexing region A method and system for using half-duplex base stations and half-duplex nodes in a Frequency Division Duplexing region to provide wireless connectivity between the half-duplex base stations and customers in multiple sectors of a cell. The method and system can use t... | 03/04/2008 |
| 7333496 | System and method for indicating the priority of voice over internet protocol (VoIP) calls A method for indicating the priority of a Voice Over Internet Protocol (VoIP) call includes receiving a dialed number for a connection, generating a call set up request including the dialed number, receiving a priority for the call based on user input provided conte... | 02/19/2008 |
| 7330952 | Integrated circuit memory device having delayed write timing based on read response time An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermin... | 02/12/2008 |
| 7330953 | Memory system having delayed write timing A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrate... | 02/12/2008 |
| 7321586 | Method for establishing communication links in an exchange in a switching system The present invention relates to a method wherein communication links between subscriber access lines of subscriber access units of an exchange in a switching system comprising a number of exchanges are established within the exchange concerned either directly in th... | 01/22/2008 |
| 7317725 | System and method for implementing combined packetized TDM streams and TDM cross connect functions Apparatus implements combined packetized time-division multiplexed (TDM) streams and TDM cross connect functions. The apparatus includes an input buffer, a reassembly state machine, a frame buffer, and a segmentation state machine. The frame buffer includes multiple... | 01/08/2008 |
| 7310319 | Multiple-domain processing system using hierarchically orthogonal switching fabric A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system. ... | 12/18/2007 |
| 7310276 | Memory device and method having data path with multiple prefetch I/O configurations A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to... | 12/18/2007 |
| 7295554 | Word Multiplexing of encoded signals into a higher bit rate serial data stream A method of data communication that includes receiving a plurality of 8b/10b encoded data streams. The method also includes multiplexing, on a word by word basis, each of the plurality of data streams and forming a new encoded data stream. The method also includes g... | 11/13/2007 |
| 7295817 | Wireless data communication unit A wireless data communication unit (700) shares a data communication resource with a plurality of other data communication units. The wireless data communication unit (700) receives channel status information from a wireless serving communication unit ... | 11/13/2007 |
| 7289508 | Systems and methods for processing any-to-any transmissions A data processing system performs any-to-any transmission of data blocks. The system receives the data blocks on incoming data streams, and load balances the data blocks across a number of processing paths. The processing paths process the data blocks causing one or... | 10/30/2007 |
| 7287119 | Integrated circuit memory device with delayed write command processing An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to ... | 10/23/2007 |
| 7280481 | Shortest path search method “Midway” A method of searching for a shortest path from a single source node to a single destination node in a two dimensional computer network. The method is similar to Dijkstra shortest path algorithm (“Dijkstra”) in the way it builds a shortest path tree. However, ins... | 10/09/2007 |
| 7274689 | Packet switch with one-stop buffer in memory with massive parallel access A broadband packet switch that handles all packets that arrive within the same frame time by simultaneously bit-pipelining the packets into different sections of the one-stop packet buffer through an input switch. Each packet remains in is selected section until its... | 09/25/2007 |
| 7274691 | Network switch with packet scheduling An apparatus and method for switching data packet flows by assigning schedules to guaranteed delay and bandwidth traffic. Scheduled bandwidth is subtracted from the available bandwidth, and the remaining unscheduled bandwidth is available for standard “best-effort... | 09/25/2007 |
| 7248583 | Parallel and iterative algorithm for switching data packets The invention relates to a packet switching device with a plurality of input and output ports and at least one switching unit (3 to 5) comprising a coupling matrix and an arbiter unit (9) for controlling the coupling matrix (8), wherein | 07/24/2007 |
| 7243183 | SONET data byte switch A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices is disclosed. The memory devices include a first memory bank configur... | 07/10/2007 |
| 7237135 | Cyclemaster synchronization in a distributed bridge A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon occurrence of a cycle synchronization event on the local portal; the pe... | 06/26/2007 |
| 7215665 | Apparatus for switching time division multiplex channels A time division multiplex switching apparatus is provided for switching channels from any number of input data streams, each of which may have any of a plurality of data rates, to any of a plurality of output data streams, each of which may likewise have any one of ... | 05/08/2007 |
| 7212523 | Pipeline architecture for the design of a single-stage cross-connect system An architecture for a high bandwidth digital cross-connect switching system that is internally non-blocking, has a simpler layout, and employs a reduced number of logic gates. The high bandwidth digital cross-connect switching architecture comprises a Time Division ... | 05/01/2007 |
| 7197611 | Integrated circuit memory device having write latency function A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or... | 03/27/2007 |
| 7191388 | Fast diagonal interleaved parity (DIP) calculator A method of calculating a diagonal interleaved parity word for groups of words sampled from a bus is provided, wherein a predetermined number of words are included in each sampling cycle. The bus carries successive data words that are followed by a control word. At ... | 03/13/2007 |
| 7187673 | Technique for creating a machine to route non-packetized digital signals using distributed RAM A signal router routes N inputs to M outputs. All inputs signals are ultimately applied to a data buss by spreading across multiple buss lines and time multiplexing. The data are read from the buss and written in identical images to K random access memories. The mem... | 03/06/2007 |
| 7180913 | Transparent error count transfer method and apparatus It is proposed that currently unused portions of transport overhead in frames sent on a high-speed outgoing channel be used to carry error count information from each of four low-speed input channels. At a 4:1 combiner, error monitoring bytes are extracted from tran... | 02/20/2007 |
| 7177314 | Transmit virtual concatenation processor A transmit virtual concatenation processor for multiplexing channelized data onto a SONET/SDH frame is disclosed. The processor is scalable and is able to handle mapping a number of data channels to a number of different frame sizes including STS-12, STS-48, STS-192... | 02/13/2007 |
| 7161906 | Three-stage switch fabric with input device features A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations.... | 01/09/2007 |
| 7158528 | Scheduler for a packet routing and switching system In one embodiment, queues associated with a first traffic class (FTC) are selected for service. Each FTC queue having at least one enqueued cell is identified as an occupied FTC queue, Where at least one FTC queue is provisioned for burst scheduling of multiple cell... | 01/02/2007 |
| 7158517 | Method and apparatus for frame-based protocol processing A method and apparatus for an overhead processing system is described. More particularly, frame latency is used to process less time-critical overhead with the overhead processing system. Such a system uses less semiconductor wafer area and consumes less power than ... | 01/02/2007 |
| 7154887 | Non-blocking grooming switch A grooming switch comprises plural input ports for receiving multi-time-slot input signals and plural output ports for forwarding multi-time-slot output signals. At least five switching stages alternate between time switching and space switching. The first stage is ... | 12/26/2006 |
| 7151707 | Memory device and method having data path with multiple prefetch I/O configurations A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel t... | 12/19/2006 |
