Quotables
"There is no reason anyone would want a computer in their home."
Ken Olsen, chairman and founder of Digital Equipment Corporation ; 1977
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8050148 | Flash time stamp apparatus One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside the DLL. An output of each of the delay elements is con... | 11/01/2011 |
| 7961559 | Duty cycle measurement circuit for measuring and maintaining balanced clock duty cycle A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The regis... | 06/14/2011 |
| 7710835 | High resolution time detecting apparatus using interpolation and time detecting method using the same A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of d... | 05/04/2010 |
| 7525878 | Time measuring circuit with pulse delay circuit In a time measuring circuit, a pulse delay circuit is provided with a plurality of delay units. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A... | 04/28/2009 |
| 7400555 | Built in self test circuit for measuring total timing uncertainty in a digital data path A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) cl... | 07/15/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7373538 | Method for determining interconnect line performance within an integrated circuit A method for determining propagation delay differences for conductive lines of an integrated circuit is described. A first path is formed by coupling a first portion of conductive lines together. The first portion is associated with a first region of the integrated ... | 05/13/2008 |
| 7363560 | Circuit for and method of determining the location of a defect in an integrated circuit According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of t... | 04/22/2008 |
| 7362659 | Low current microcontroller circuit A method and system for accurate timing in a low current system useful in fuzing applications generates a first count of oscillations of an oscillator of unknown frequency during a first period of unknown duration. A second count of oscillations of the oscillator is... | 04/22/2008 |
| 7339853 | Time stamping events for fractions of a clock cycle Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals ... | 03/04/2008 |
| 7327179 | Pulse generator, optical disk writer and tuner A pulse generator is provided for generating pulses with a selectable variable width and/or delay. The pulse generator comprises an oscillator and a selecting arrangement for selecting how many of a first group of delay elements are connected in series for delaying ... | 02/05/2008 |
| 7315489 | Method and apparatus for time measurement A method is provided for accurate time measurement. Time is first measured with a first oscillator. At designated intervals, a second oscillator is activated for a period of time based on the first oscillator. The second oscillator is more accurate than the first os... | 01/01/2008 |
| 7315270 | Differential delay-line analog-to-digital converter Differential delay-line analog-to-digital (A/D) converters for use in current and power sensing applications are provided. These A/D converters are well suited for a wide range of electronic applications, including over-load protection, current mode control, current... | 01/01/2008 |
| 7304510 | Digital phase detector improving phase detection resolution thereof A digital phase detector has a plurality of first delay elements through which a first clock is delayed, a plurality of second delay elements through which a second clock is delayed, and a plurality of data holding circuits. The data holding circuits latch the first... | 12/04/2007 |
| 7279944 | Clock signal generator with self-calibrating mode A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for... | 10/09/2007 |
| 7274236 | Variable delay line with multiple hierarchy Disclosed herein are improved, simplified designs for a hierarchical delay line (HDL). The HDL is useful in providing precise phase control between an input clock signal and an output clock signal, and has particular utility as the variable delay in a delay-locked l... | 09/25/2007 |
| 7260754 | Semiconductor device with speed binning test circuit and test method thereof A speed binning test circuit for a semiconductor device may include a plurality of circuit groups arranged along a boundary of a chip circuit. Each circuit group may include a different number of unit delay circuits that may form a chain structure. The speed binning... | 08/21/2007 |
| 7259608 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/21/2007 |
| 7253672 | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled ... | 08/07/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7228464 | PICA system timing measurement and calibration PICA probe system apparatus is described, including apparatus for calibrating an event timer having a coarse measurement capability in which time intervals defined by clock boundaries are counted and a fine measurement capability in which time between boundaries is ... | 06/05/2007 |
| 7219269 | Self-calibrating strobe signal generator A self-calibrating strobe signal generator for a BIST circuit responds to an edge of an input strobe signal by generating corresponding edges of first and second strobe signals separated in time by a target delay specified by input data. The strobe signal generator ... | 05/15/2007 |
| 7216047 | Time-delay discriminator A method of determining the delay between two corresponding noise-like signals comprises determining events at which the level of a first of the signal crosses a predetermined threshold, using each event to sample a second signal, combining the samples to produce an... | 05/08/2007 |
| 7203859 | Variable clock configuration for switched op-amp circuits A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the individual operational amplifiers. The length of the off-phase can be adapted ... | 04/10/2007 |
| 7188289 | Test circuit and circuit test method The test circuit tests a test target circuit and outputs a test result to a tester. The test circuit includes a first clock generator, a second clock generator, a test target circuit, a BIST circuit for performing the test, and a tester synchronous circuit. The BIST... | 03/06/2007 |
| 7180970 | Automatic link establishment using external synchronization A system and method for synchronized communication of information between transmitting and receiving stations. The system has a first station and a second station, each attached to a modem, and a device, such as an automated link establishment controller, for establ... | 02/20/2007 |
| 7178113 | Identification of an integrated circuit from its physical manufacture parameters The invention concerns an identification method and circuit (1) of the network type of parameters contained in an integrated circuit chip, comprising a single input terminal (2) for applying a signal (E) triggering an identification, the output termina... | 02/13/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7120817 | Method of signal distribution based on a standing wave within a closed loop path A closed-loop based timing signal distribution architecture includes at least one signal source coupled to a signal path disposed in a closed loop arrangement to facilitate generation of a standing wave signal within the signal path. In one embodiment, at least one ... | 10/10/2006 |
| 7102401 | Measuring the 3 dB frequency bandwidth of a phase-locked loop The 3 dB frequency bandwidth of a phase-locked loop (PLL) is determined by measuring the frequency of a voltage controlled oscillator (VCO) signal when an up charging current is applied, measuring the frequency of the VCO signal when a down charging current is appli... | 09/05/2006 |
| 7095265 | PVT-compensated clock distribution Described are methods and systems for distributing low-skew, predictably timed clock signals. A clock distribution network includes a plurality of dynamically adjustable clock buffers. A control circuit connected to each clock buffer controls the delays through the ... | 08/22/2006 |
| 7084686 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/01/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
| 7078951 | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled ... | 07/18/2006 |
| 7075447 | Secure time measurement electronic device and method An electronic circuit comprising a first counter clocked by a clock signal provided to have a first period and provided by an oscillator external to the circuit, and comprising a second counter clocked with a second period by an oscillator internal to the circuit, t... | 07/11/2006 |
| 7068089 | Digitally programmable I/Q phase offset compensation Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective... | 06/27/2006 |
| 7050516 | System and method for periodic noise avoidance in data transmission systems A system for periodic noise avoidance including a timing discriminator receiving an input signal from a communications channel. The input signal includes data packets and empty slots with periodic noise. The timing discriminator outputs a first error measurement of ... | 05/23/2006 |
| 7046062 | Method and device for symmetrical slew rate calibration A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A... | 05/16/2006 |
| 7034592 | Clock controlling method and circuit A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and... | 04/25/2006 |
