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| Number | Title | Issue Date |
| 7405465 | Deposited semiconductor structure to minimize n-type dopant diffusion and method of making In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thic... | 07/29/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7154321 | Digital delay line A digital delay line including a first feedback delay line having a first number of interlinked first delay elements, at least one second feedback counter having a second number of second interlinked counting elements, the counting elements being clocked by one of t... | 12/26/2006 |
| 5612964 | High performance, fault tolerant orthogonal shuffle memory and method A high performance fault tolerant orthogonal shuffle memory comprising a plurality of memory cells arranged to form a two-dimensional array of rows and columns. Each memory cell includes a data store element for storing data and a multi-state data transmi... | 03/18/1997 |
| 4961169 | Method of and apparatus for generating variable time delay A variable length shift register comprises a memory cell array (1) having memory cells arranged in a matrix of row and columns, a variable length ring pointer (2) responsive to a bit length selecting signal for sequentially activating a single row in the ... | 10/02/1990 |
| 4905196 | Method and storage device for saving the computer status during interrupt In order to reduce the down time of a computer (1, 4-8) caused by a fault or interrupt in the program run, program recovery points are provided which are time-dependent or can be preset in the main program of a useful program, and when these recovery poin... | 02/27/1990 |
| 4890261 | Variable word length circuit of semiconductor memory A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift register is connected to the output of the last stage and regio... | 12/26/1989 |
| 4862419 | High speed pointer based first-in-first-out memory A FIFO memory system organizes a memory with N word storage locations into M pointer-based random access memories, each containing N/M storage locations. A sequence of data words is written into and read out of the M RAMs in a cyclical fashion. An M fold ... | 08/29/1989 |
| 4796225 | Programmable dynamic shift register with variable shift control The invention relates to a shift register structure and its control. The positioning and/or synchronization of data contained in this register for the purpose of serial operation are essentially obtained by acquisition of data on at least one auxiliary ou... | 01/03/1989 |
| 4202046 | Data storage system for storing multilevel signals A data storage system for storing multilevel, non-binary data includes a charge coupled device (CCD) shift register and a detection circuit for detecting the data level represented by the charge or signal within each cell location of the CCD shift registe... | 05/06/1980 |
| 4185324 | Data storage system A data storage system having a charge coupled device (CCD) shift register and a detection circuit for detecting the binary value represented by the charge level or signal within each cell location of the CCD shift register. The detection circuit includes ... | 01/22/1980 |
| 4085459 | Multivalued data memory system using a charge coupled element A memory system includes means for injecting a multivalued signal with at least three information carrying voltage levels, in the form of electric charge, to a charge coupled device (CCD); and a detection means for detecting a multivalued signal level rea... | 04/18/1978 |
| 3992699 | First-in/first-out data storage system A first-in/first-out memory device has a shift register with a storage capacity of n stages in which data units can be stored, and a modulo-n address counter having one state representing each stage of the shift register. In one embodiment designed for fa... | 11/16/1976 |
