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| Number | Title | Issue Date |
| 7804700 | Semiconductor memory device with reduced coupling noise A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory eleme... | 09/28/2010 |
| 7414913 | Bitline twisting scheme for multiport memory A multiport memory in one embodiment of the invention includes a memory cell array, where each column in the array has two exterior complementary bitline pairs and zero, one, or more interior complementary bitline pairs. Across each pair of adjacent columns in the a... | 08/19/2008 |
| 7372091 | Selective epitaxy vertical integrated circuit components Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of t... | 05/13/2008 |
| 7349232 | 6FDRAM cell design with 3F-pitch folded digitline sense amplifier The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality o... | 03/25/2008 |
| 7310256 | Semiconductor memory device A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing informa... | 12/18/2007 |
| 7286437 | Three dimensional twisted bitline architecture for multi-port memory A memory array of dual part cells has a pair of twisted write bitlines and a pair of twisted read bitlines for each column. The twist is made by alternating the vertical position of each bitline pair in each section of a column, with the result of generating common ... | 10/23/2007 |
| 7277330 | Nonvolatile semiconductor memory device having improved redundancy relieving rate In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the ... | 10/02/2007 |
| 7277309 | Interlocking memory/logic cell layout and method of manufacture A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic por... | 10/02/2007 |
| 7257011 | Semiconductor memory having twisted bit line architecture A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a fi... | 08/14/2007 |
| 7242602 | Semiconductor memory devices having conductive line in twisted areas of twisted bit line pairs A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend... | 07/10/2007 |
| 7227768 | Power interconnect structure for balanced bitline capacitance in a memory array According to one exemplary embodiment, a semiconductor die includes a memory core array situated over a substrate, where the memory core array includes a number of bitlines, where the bitlines can be situated in a first interconnect metal layer in the semiconductor ... | 06/05/2007 |
| 7224626 | Redundancy circuits for semiconductor memory A semiconductor random access memory device has an array of normal memory and an array of dummy memory cells. The array of the dummy memory cells are controlled in order to form a redundant twin-cell structure that includes at least one of the dummy memory cells. | 05/29/2007 |
| 7221577 | Bus twisting scheme for distributed coupling and low power The present invention relates to a system and method for equalizing the capacitance between/among n lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the n lines using an algorithm for ... | 05/22/2007 |
| 7200059 | Semiconductor memory and burn-in test method of semiconductor memory A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit lin... | 04/03/2007 |
| 7154793 | Integrated memory and method for functional testing of the integrated memory An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of switches. The memory contains column select lines. One of the column... | 12/26/2006 |
| 7145376 | Method and circuitry for reducing duty cycle distortion in differential delay lines A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may... | 12/05/2006 |
| 7139993 | Method and apparatus for routing differential signals across a semiconductor chip One embodiment of the present invention provides an arrangement of differential pairs of wires that carry differential signals across a semiconductor chip. In this arrangement, differential pairs of wires are organized within a set of parallel tracks on the semicond... | 11/21/2006 |
| 7116591 | Redundancy circuits and memory devices having a twist bitline scheme and methods of repairing defective cells in the same Redundancy circuits are provided for an integrated circuit memory device including a first memory cell block including a plurality of primary wordlines and a spare wordline, each associated with a plurality of memory cells; a second memory cell block including a plu... | 10/03/2006 |
| 7106639 | Defect management enabled PIRM and method A defect management enabled PIRM including a data storage medium providing a plurality of cross point data storage arrays. Each array provides a plurality of memory cells. The arrays are allocated into separate super arrays, the separate super arrays virtually align... | 09/12/2006 |
| 7079410 | Ferroelectric memory cell array and device for operating the same A ferroelectric memory cell array and a device for driving the same are disclosed, in which the ferroelectric memory cell array is defined as first and second cell regions each using at least one group of four split wordlines to reduce a layout area of the memory ce... | 07/18/2006 |
| 7075807 | Magnetic memory with static magnetic offset field A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free... | 07/11/2006 |
| 7045834 | Memory cell arrays A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted port... | 05/16/2006 |
| 7042749 | Stacked 1T-nmemory cell structure This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the h... | 05/09/2006 |
| 7031214 | Digital multilevel memory system having multistage autozero sensing A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment ref... | 04/18/2006 |
| 7020012 | Cross point array using distinct voltages Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely d... | 03/28/2006 |
| 7005695 | Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received the... | 02/28/2006 |
| 6999336 | Ferroelectric memory A memory cell array includes ferroelectric memory cells arranged in m rows and n columns, bit lines provided along a row direction, and word lines and plate line provided along a column direction. The word lines are provided side by side so as to intersect each othe... | 02/14/2006 |
| 6995419 | Semiconductor constructions having crystalline dielectric layers The invention includes semiconductor constructions. In one implementation, semiconductor construction includes a first conductive material. A first layer of a dielectric material is over the first conductive material. A second layer of the dielectric material is on ... | 02/07/2006 |
| 6992343 | Semiconductor memory device A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a pe... | 01/31/2006 |
| 6912696 | Smart card and circuitry layout thereof for reducing cross-talk A semiconductor integrated circuit includes a ROM having bit lines extending in a first direction in a first layer. A conductive line is arranged in a second layer above the first layer, extending in a second direction, which is orthogonal to the first direction, ac... | 06/28/2005 |
| 6909663 | Multiport memory with twisted bitlines Memory cell arrays are defined by rows and columns of memory cells that are addressed by sets of bitlines associated with a first memory port and a second memory port. The bitlines associated with the first memory port have bitline exchanges associated with a first ... | 06/21/2005 |
| 6894231 | Bus twisting scheme for distributed coupling and low power The present invention relates to a system and method for equalizing the capacitance between at least two lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the lines using an algorithm. ... | 05/17/2005 |
| 6873537 | Ferroelectric memory cell array and device for operating the same A ferroelectric memory cell array and a device for driving the same are disclosed, in which the ferroelectric memory cell array is defined as first and second cell regions each using at least one group of four split wordlines to reduce a layout area of the memory ce... | 03/29/2005 |
| 6870754 | Ferroelectric memory A memory cell array includes ferroelectric memory cells arranged in the form of m rows and n columns, bit lines provided along a row direction, and word lines and plate lines provided along a column direction. The word lines are provided side by side so as to inters... | 03/22/2005 |
| 6862204 | Semiconductor integrated circuit having connecting wires for interconnecting bit lines A plurality of memory cell arrays includes bit lines and memory cells each constituted by a variable capacitor, and operates at mutually different timings. The bit lines of each memory cell array are connected to bit lines of the other memory cell arrays via connect... | 03/01/2005 |
| 6862234 | Method and test circuit for testing a dynamic memory circuit Method and system for testing a sense amplifier in a dynamic memory circuit. In one embodiment, the sense amplifier is connected to a first bit line pair via a first switching device and to a second bit line pair via a second switching device. First memory cells are... | 03/01/2005 |
| 6845028 | Semiconductor memory device using open data line arrangement When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense ampl... | 01/18/2005 |
| 6839266 | Memory module with offset data lines and bit line swizzle configuration A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected t... | 01/04/2005 |
| 6831854 | Cross point memory array using distinct voltages Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines uniquely definin... | 12/14/2004 |
| 6826075 | Random access semiconductor memory with reduced signal overcoupling A memory matrix has at least one cell array including column lines and row lines. Memory elements are situated at points where the row lines and column lines intersect one another. In each case two adjacent lines are guided such that they cross one another in such a... | 11/30/2004 |
