Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 7176714 | Multiple data rate memory interface architecture The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks. | 02/13/2007 |
| 6769041 | Method and apparatus for providing bimodal voltage references for differential signaling According to an embodiment of the invention, systems, apparatus and methods are disclosed for providing bimodal voltage references for use in differential signaling between components or devices. According to an embodiment, a switchable power supply is used to produ... | 07/27/2004 |
| 6483766 | Interface circuit for using in high-speed semiconductor device and interfacing method The present invention discloses an interface circuit suitable for a high-speed semiconductor device. The interface circuit includes an input driver producing a first and second output signal having opposite phases to each other by receiving an external po... | 11/19/2002 |
| 6018492 | Semiconductor memory device A semiconductor memory device is grouped into a plurality of flexible macro chips. Under the circumstances, a clock input first stage circuit is arranged in a first flexible macro chip to supply an internal reference clock signal and a first internal cloc... | 01/25/2000 |
| 5103426 | Decoding circuit and method for functional block selection An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when ... | 04/07/1992 |
| 4972380 | Decoding circuit for functional block An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when ... | 11/20/1990 |
| 4845678 | Memory comprising simultaneously addressable memory elements A random access memory (1) is described in which one address of a row of addresses is activatable. There is also realized a block addressing mode in which all addresses between a selectable first address and a selectable second address are activated. To t... | 07/04/1989 |
