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| Number | Title | Issue Date |
| 8111536 | Semiconductor memory device The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The res... | 02/07/2012 |
| 8111535 | Presetable RAM A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be pr... | 02/07/2012 |
| 8107271 | Termination circuits and semiconductor memory devices having the same A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding... | 01/31/2012 |
| 8098509 | Nonvolatile semiconductor memory device, method of fabricating the nonvolatile semiconductor memory device and process of writing data on the nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of seco... | 01/17/2012 |
| 8098508 | Configurable inputs and outputs for memory stacking system and method Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablemen... | 01/17/2012 |
| 8094478 | Nonvolatile memory device having a plurality of memory blocks A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously bet... | 01/10/2012 |
| 8089795 | Memory module with memory stack and interface with enhanced capabilities A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated ci... | 01/03/2012 |
| 8089796 | Information recording and reproducing device According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first and second layers and is capable of reversibly transitioning between a first ... | 01/03/2012 |
| 8068357 | Memory controller with multi-modal reference pad A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The re... | 11/29/2011 |
| 8064238 | System using non-volatile resistivity-sensitive memory for emulation of embedded flash memory Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity pro... | 11/22/2011 |
| 8059441 | Memory array on more than one die For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the me... | 11/15/2011 |
| 8059442 | ROM array with shared bit-lines Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with... | 11/15/2011 |
| 8050072 | Dual stage sensing for non-volatile memory A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying... | 11/01/2011 |
| 8050073 | Semiconductor memory device A semiconductor memory device includes a memory block having first and second word lines extending in a first direction and bit lines extending in a perpendicular second direction; a first driver region at a side of the memory block in the first direction driving th... | 11/01/2011 |
| 8045356 | Memory modules having daisy chain wiring configurations and filters Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory... | 10/25/2011 |
| 8040710 | Semiconductor memory arrangement A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is di... | 10/18/2011 |
| 8036012 | Device for controlling the activity of modules of an array of memory modules A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective me... | 10/11/2011 |
| 8036011 | Memory module for improving signal integrity and computer system having the same A memory module includes a plurality of buses and a plurality of memory chips arranged close to each other along each of the plurality of buses. An N-th memory chip, where N is an integer, of the plurality of memory chips is connected to any one of the plurality of ... | 10/11/2011 |
| 8018753 | Memory module including voltage sense monitoring interface Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second... | 09/13/2011 |
| 8014184 | Radiation hardened memory cell A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is c... | 09/06/2011 |
| 8004870 | Memory chips and judgment circuits thereof A memory chip is provided. The memory chip operates at modes and includes an option pad and a judgment circuit. The judgment circuit is coupled to the option pad generates a judgment signal according to the current status of the option pad. The judgment signal indic... | 08/23/2011 |
| 8000123 | Semiconductor memory device of open bit line type There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at l... | 08/16/2011 |
| 7995366 | Homogenous cell array A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently... | 08/09/2011 |
| 7990747 | Semiconductor chip and semiconductor device There are provided a semiconductor device and a semiconductor chip, in which the interconnection is made to be highly reliable by stacking three or more layers of chips without contact therebetween. A semiconductor chip of the present invention comprises a first sig... | 08/02/2011 |
| 7990746 | Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activati... | 08/02/2011 |
| 7986542 | Semiconductor memory apparatus A semiconductor memory that includes a row decoder part, a first cell array placed on either side of the row decoder part, a second cell array placed on the other side of the row decoder part, and a wiring layer that short-circuits word lines corresponding to a spec... | 07/26/2011 |
| 7986541 | Integrated circuit device and electronic instrument An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory includes a plurality of RAM blocks, each of the RAM blocks i... | 07/26/2011 |
| 7978492 | Integrated circuit incorporating decoders disposed beneath memory arrays A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus ... | 07/12/2011 |
| 7978491 | Stacked memory cell structure and method of forming such a structure This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the h... | 07/12/2011 |
| 7969761 | Semiconductor memory device, memory device support and memory module In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the f... | 06/28/2011 |
| 7969760 | Semiconductor memory device and manufacturing method of the same The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed... | 06/28/2011 |
| 7965533 | Semiconductor device including plurality of parallel input/output lines and methods of fabricating and using the same Provided are semiconductor devices and methods for fabricating and using the semiconductor devices, wherein the semiconductor devices may include a first element, a second element, and a plurality of parallel IO lines connecting the first element with the second ele... | 06/21/2011 |
| 7965532 | Enhanced performance memory systems and methods Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus commu... | 06/21/2011 |
| 7952901 | Content addressable memory A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell ... | 05/31/2011 |
| 7948787 | Semiconductor memory device A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit h... | 05/24/2011 |
| 7944725 | Semiconductor memory and method for operating a semiconductor memory A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bi... | 05/17/2011 |
| 7944726 | Low power termination for memory modules An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel... | 05/17/2011 |
| 7940544 | Memory system having multiple vias at junctions between traces An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces co... | 05/10/2011 |
| 7936579 | Semiconductor memory device and semiconductor device group A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semi... | 05/03/2011 |
| 7933134 | Semiconductor memory device having a plurality of chips and capability of outputting a busy signal One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy ... | 04/26/2011 |
