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| Number | Title | Issue Date |
| 7663902 | Memory device in which data is written or read by a switching operation of a bit line that is inserted into a trench formed between a plurality of word lines A memory device and a method for fabricating the same provide a device capable of increasing or maximizing the performance of a microstructure device. The device includes: a plurality of word lines formed with a gap therebetween and extending in parallel with each o... | 02/16/2010 |
| 7663903 | Semiconductor memory device having improved voltage transmission path and driving method thereof Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more se... | 02/16/2010 |
| 7660141 | Layout structures and methods of fabricating layout structures Example embodiments may provide a layout structure and layout method for a memory device that may reduce the area of the memory device. Example embodiment layout structures may include a first region and/or a second region. First and second sensing MOS transistors o... | 02/09/2010 |
| 7656693 | Semiconductor device and manufacturing method thereof In a memory cell area of a semiconductor device, first, second, and third inter-layer insulating films respectively cover a cell transistor, a bit wiring line, and a capacitor which are connected to each other. In an adjacent peripheral circuit area, a peripheral-ci... | 02/02/2010 |
| 7652905 | Flash memory array architecture A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share t... | 01/26/2010 |
| 7636250 | Random access memory that selectively provides data to amplifiers A random access memory including a first amplifier, a second amplifier, a first data path, a second data path, and a first circuit. The first data path receives first data via first memory cells and the second data path receives second data via second memory cells. ... | 12/22/2009 |
| 7633786 | Couplings within memory devices and methods Methods and apparatus are provided. A memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiple... | 12/15/2009 |
| 7630224 | Semiconductor integrated circuit device and layout method thereof A semiconductor integrated circuit device includes a memory macro and M (M is an integer more than 1) passage wirings. The memory macro includes a memory cell array comprising memory cells which are arranged in a matrix, digit line pairs connected with the memory ce... | 12/08/2009 |
| 7630223 | Memory device and method of arranging signal and power lines A memory device and method for arranging signal and power lines includes a plurality of sub-memory cell arrays having a plurality of memory cells, a plurality of sense amplifiers to sense and amplify data from the plurality of memory cells, a plurality of power line... | 12/08/2009 |
| 7623365 | Memory device interface methods, apparatus, and systems Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a... | 11/24/2009 |
| 7619913 | Device, method and program for managing area information In an apparatus for managing area data, the first data structure for area management includes: a first index data structure including a first root node corresponding to a first set of areas containing a first area, first non-leaf nodes, and first leaf nodes; and a f... | 11/17/2009 |
| 7613022 | Semiconductor memory device and method of forming the same Example embodiments provide a semiconductor memory device and method of forming a semiconductor memory device that may equalize load due to a coupling capacitance between a line and a component signal when the line intersects the component signal in a memory cell ar... | 11/03/2009 |
| 7613026 | Apparatus and methods for optically-coupled memory systems Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module ... | 11/03/2009 |
| 7613024 | Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit ... | 11/03/2009 |
| 7613025 | Dram cell design with folded digitline architecture and angled active areas The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6 F2 is disclosed which has a plurality ... | 11/03/2009 |
| 7613023 | Memory arrangement, particularly for the non-volatile storage of uncompressed video and/or audio data When recording uncompressed video and/or audio data using a digital video recorder, there is the need for a robust memory arrangement based on non-volatile, integrated circuits which is able to be fitted directly on the video camera without a long external cable con... | 11/03/2009 |
| 7609538 | Logic process DRAM A semiconductor integrated circuit device includes a dynamic random access memory (DRAM) unit. The DRAM unit comprises a plurality of bit line pairs. Each bit line pair includes a first bit line and a second bit line. The first bit line and the second bit line withi... | 10/27/2009 |
| 7606056 | Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and t... | 10/20/2009 |
| 7606057 | Metal line layout in a memory cell A memory cell includes polysilicon gates 2 running in a first direction. A sequence of layers metal lines includes a layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed by data lines 6 runn... | 10/20/2009 |
| 7602630 | Configurable inputs and outputs for memory stacking system and method Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablemen... | 10/13/2009 |
| 7599205 | Methods and apparatus of stacking DRAMs Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards. ... | 10/06/2009 |
| 7596011 | Logic process DRAM An integrated circuit device comprises a plurality of bit line pairs. First and second bit lines are aligned with each other in an end-to-end arrangement. The first and second bit lines are arranged consecutively adjacent to one another, respectively. A plurality of... | 09/29/2009 |
| 7583524 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a plurality of 3-dimensional cell arrays to reduce the chip size. The nonvolatile semiconductor memory device includes a unit block cell array including a plurality of vertically multi-layered cell arrays each inclu... | 09/01/2009 |
| 7580273 | Digital memory with controllable input/output terminals Methods and apparatus for controlling an input/output (I/O) driver of an I/O terminal based at least in part on the values being provided to the I/O terminal is disclosed. In various embodiments, a detector is employed. The detector shuts off power to the I/O driver... | 08/25/2009 |
| 7577010 | Integrated circuits, methods for manufacturing integrated circuits, integrated memory arrays The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays. ... | 08/18/2009 |
| 7573733 | Self-identifying stacked die semiconductor components A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die st... | 08/11/2009 |
| 7570504 | Device and method to reduce wordline RC time constant in semiconductor memory devices A semiconductor memory device and a method of making and using a semiconductor memory device containing a word line design, which is used in ultra-large scale integrated (ULSI) circuits, that produces a device with a lower RC time constant than devices formed using ... | 08/04/2009 |
| 7564726 | Semiconductor memory device A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a... | 07/21/2009 |
| 7558097 | Memory having bit line with resistor(s) between memory cells For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plural... | 07/07/2009 |
| 7554830 | Semiconductor device with non-volatile memory and random access memory A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-vol... | 06/30/2009 |
| 7551467 | Memory device architectures and operation Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compa... | 06/23/2009 |
| 7551477 | Multiple bit line voltages based on distance An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with... | 06/23/2009 |
| 7551468 | 276-pin buffered memory module with enhanced fault tolerance A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a... | 06/23/2009 |
| 7551466 | Bit line coupling The invention provides methods and apparatus. Alternate bit-line pairs of a memory device are concurrently selected. Each bit-line pair has one bit line formed at a first vertical level and one adjacent bit line formed at a second vertical level different than the f... | 06/23/2009 |
| 7545663 | Semiconductor storage device Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circui... | 06/09/2009 |
| 7545664 | Memory system having self timed daisy chained memory chips A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain o... | 06/09/2009 |
| 7542324 | FPGA equivalent input and output grid muxing on structural ASIC memory The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The memory interface has a first set of lines and a second set of lines. T... | 06/02/2009 |
| 7542323 | Semiconductor memory device having a plurality of chips and capability of outputting a busy signal One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy ... | 06/02/2009 |
| 7539035 | Memory system capable of changing configuration of memory modules A memory system is disclosed with first, second, and third connectors located on a system board, the third connector including pins connected to the pins of the first and second connectors through channels, and a memory controller connected to the pins of the third ... | 05/26/2009 |
| 7539036 | Semiconductor memory device including plurality of memory mats A semiconductor memory device includes a plurality of memory mats each including a memory cell storing data, a sense latch portion performing detection of data stored by the memory cell, and a buffer circuit externally outputting read data detected by the sense latc... | 05/26/2009 |