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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 7924591 | Memory device with shielding plugs adjacent to a dummy word line thereof A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate ... | 04/12/2011 |
| 7791920 | Active shielding for a circuit comprising magnetically sensitive materials The present invention provides a method for providing magnetic shielding for a circuit comprising magnetically sensitive materials, comprising actively shielding the circuit from a disturbing magnetic field. A corresponding semiconductor device is also provided. The... | 09/07/2010 |
| 7593247 | Electronic memory device having high integration density non-volatile memory cells and a reduced capacitive coupling A flash NAND electronic memory device includes non-volatile cells having a high integration density and a relative programming method. The memory device is integrated on a semiconductor substrate and includes a matrix with word lines and bit lines organized in secto... | 09/22/2009 |
| 7545662 | Method and system for magnetic shielding in semiconductor integrated circuit A circuit with an inter-module radiation interference shielding mechanism is disclosed. The circuit includes a circuit module producing a radiation field. At least one radiation shielding module is situated between the circuit module and another module that is vulne... | 06/09/2009 |
| 7535742 | Biasing and shielding circuit for source side sensing memory A shielding circuit for preventing a sense current of a target cell from the influence of a source current of first adjacent cell includes a pre-discharge device, first and second biasing units, first and second voltage pull-down units, and a connection units. The p... | 05/19/2009 |
| 7474547 | Active shielding for a circuit comprising magnetically sensitive materials Magnetic shielding is provided using a variety of methods, systems, devices and circuits. Aspects of present invention provide a method for providing magnetic shielding for a circuit comprising magnetically sensitive materials. The circuit is actively shielded from ... | 01/06/2009 |
| 7430150 | Method and system for providing sensing circuitry in a multi-bank memory device A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The metho... | 09/30/2008 |
| 7391637 | Semiconductor memory device with high permeability composite films to reduce noise in high speed interconnects A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating materia... | 06/24/2008 |
| 7335968 | High permeability composite films to reduce noise in high speed interconnects A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed ... | 02/26/2008 |
| 7327016 | High permeability composite films to reduce noise in high speed interconnects An electronic system is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating ma... | 02/05/2008 |
| 7319604 | Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell An electronic memory device with a high density of non-volatile memory cells has a reduced capacitance cell-to-cell interference. The memory cells are integrated on a semiconductor substrate and are organized in a matrix of cells with word lines and bit lines connec... | 01/15/2008 |
| 7311385 | Micro-fluid ejecting device having embedded memory device A semiconductor substrate for a micro-fluid ejecting device. The semiconductor substrate includes a plurality of fluid ejection devices disposed on the substrate. A plurality of driver transistors are disposed on the substrate for driving the plurality of fluid ejec... | 12/25/2007 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7295469 | Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse ele... | 11/13/2007 |
| 7286392 | Data retention indicator for magnetic memories The present invention provides an array (20) of magnetoresistive memory elements (10) provided with at least one data retention indicator device (50). The at least one data retention indicator device (50) comprises a first magnetic elemen... | 10/23/2007 |
| 7281667 | Method and structure for implementing secure multichip modules for encryption applications A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conduc... | 10/16/2007 |
| 7259450 | Double-packaged multi-chip semiconductor module A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices is then r... | 08/21/2007 |
| 7256098 | Method of manufacturing a memory device A method of making a memory device and a memory device is described. In one embodiment, a method of manufacturing a memory device is described. The method includes providing a substrate having a tunneling layer deposited on a main surface and having a first conducti... | 08/14/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7235457 | High permeability layered films to reduce noise in high speed interconnects This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conduc... | 06/26/2007 |
| 7227774 | MRAM integrated circuits, MRAM circuits, and systems for testing MRAM integrated circuits An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially co... | 06/05/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7203101 | Semiconductor memory device and defect remedying method thereof A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle... | 04/10/2007 |
| 7193823 | Magnetoresistive device exhibiting small and stable bias fields independent of device size variation The present invention relates generally to the magnetic information storage technology, and particularly, to magnetic recording disc drives including a sensor having a giant magnetoresistance (GMR) based spin valve structure or a tunneling magnetoresistance(TMR) bas... | 03/20/2007 |
| 7184293 | Crosspoint-type ferroelectric memory A crosspoint-type ferroelectric memory is provided. In the crosspoint-type ferroelectric memory, a first memory cell array and a second memory cell array are stacked with a first interlayer insulating layer and a second interlayer insulating layer therebetween. The ... | 02/27/2007 |
| 7166515 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between th... | 01/23/2007 |
| 7164161 | Method of formation of dual gate structure for imagers A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are produced, a silicide layer is provided over conductive layers, reducing resistance. The device can be an im... | 01/16/2007 |
| 7139184 | Memory cell array A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active ... | 11/21/2006 |
| 7126866 | Low power ROM architecture In a ROM structure, power consumption is reduced by providing for pre-discharging of only the bit line corresponding to the memory location that is being read. Column select lines are coupled to logic to switch in a pre-discharging circuit prior to reading, and to d... | 10/24/2006 |
| 7115912 | Device for defeating reverse engineering of integrated circuits by optical means An integrated circuit chip (IC) is equipped with a device for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in a circuit located in the IC. The device can be an opaque structure that blocks... | 10/03/2006 |
| 7110312 | Non-volatile magnetic memory device A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second ... | 09/19/2006 |
| 7101770 | Capacitive techniques to reduce noise in high speed interconnections Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabr... | 09/05/2006 |
| 7087950 | Flash memory cell, flash memory device and manufacturing method thereof The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said ch... | 08/08/2006 |
| 7057914 | Cross point memory array with fast access time Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. S... | 06/06/2006 |
| 7049667 | Conductive channel pseudo block process and circuit to inhibit reverse engineering A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among... | 05/23/2006 |
| 7015823 | Tamper resistant circuit boards A physical barrier for a circuit board also functions as a tampering sensor or sensors monitored by electrical circuitry that generates a tamper signal for erasing information critical for the operation of the circuit board in the event of sensed tampering. One or m... | 03/21/2006 |
| 7008873 | Integrated circuit with reverse engineering protection Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness... | 03/07/2006 |
| 7005733 | Anti tamper encapsulation for an integrated circuit An integrated circuit device comprising: a circuit which uses encryption; and an encapsulation packaging layer; in which the circuit is responsive to at least one physical parameter of the encapsulation to apply the encryption and/or decryption by reading the key th... | 02/28/2006 |
| 6999339 | Integrated circuit including sensor to sense environmental data, method of compensating an MRAM integrated circuit for the effects of an external magnetic field, MRAM integrated circuit, and method of testing An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially co... | 02/14/2006 |
| 6979606 | Use of silicon block process step to camouflage a false transistor A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is n... | 12/27/2005 |
