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The Quarterly Review ; March edition, 1825
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| Number | Title | Issue Date |
| 8125810 | Low power ternary content-addressable memory (TCAM) An integrated circuit (200) includes a semiconductor memory device (202) operative for determining match between received search data and stored data in a plurality of ternary content addressable memory (TCAM) bitcells (100). The plurality of TC... | 02/28/2012 |
| 8102690 | Bank re-assignment in chip to reduce IR drop A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the p... | 01/24/2012 |
| 8085569 | Semiconductor memory device, and multi-chip package and method of operating the same Multi-chip package devices and related data programming methods are disclosed. A multi-chip package device includes one or more memory chips and a controller. The one or more memory chips include a single level cell section and a multi level cell section. The contro... | 12/27/2011 |
| 8064237 | Identifying and accessing individual memory devices in a memory channel In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage ... | 11/22/2011 |
| 7995365 | Method and apparatuses for managing double data rate in non-volatile memory Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and synchronize a plurality of data line signals with a clock signal. The apparatus includes a selector unit that rec... | 08/09/2011 |
| 7948786 | Rank select using a global select pin Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of ... | 05/24/2011 |
| 7940543 | Low power synchronous memory command address scheme A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a lat... | 05/10/2011 |
| 7894232 | Semiconductor device having user field and vendor field A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a di... | 02/22/2011 |
| 7872892 | Identifying and accessing individual memory devices in a memory channel In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage ... | 01/18/2011 |
| 7855925 | Inter-transmission multi memory chip, system including the same and associated method A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip. ... | 12/21/2010 |
| 7852654 | Semiconductor memory device, and multi-chip package and method of operating the same The present invention relates to a semiconductor device including a MLC capable of storing plural bits of data, wherein some of the MLC are set and operated as a buffer section in response to a control signal. ... | 12/14/2010 |
| 7808805 | Column address control circuit capable of selectively enabling sense amplifier in response to column addresses A column address control circuit comprises a control unit for outputting a control signal in response to a DDR mode signal and a first signal, and an address counting unit configured to receive a start column address and output a start column address in response to ... | 10/05/2010 |
| 7787276 | Memory array using mechanical switch and method for operating thereof A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode ... | 08/31/2010 |
| 7773402 | Semiconductor memory apparatus A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first sup... | 08/10/2010 |
| 7542322 | Buffered continuous multi-drop clock ring A method, system and apparatus to distribute a clock signal among a plurality of memory units in a memory architecture. A buffer chip is coupled to a plurality of memory units each by a point to point link. The buffer chip includes a clock generator to generate a co... | 06/02/2009 |
| 7539034 | Memory configured on a common substrate A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory. ... | 05/26/2009 |
| 7515451 | Memory apparatus with a bus architecture A system comprises a board, memory units that are arranged on the board, a control unit configured to control memory access to the memory units, at least one control/address bus configured to transmit control/address signals from the control unit to a first group of... | 04/07/2009 |
| 7489534 | Semiconductor package for forming a double die package (DDP) A semiconductor package for forming a Double Die Package (DDP) with a plurality of single chips includes: a buffer configured to buffer an external address to generate a row address which is defined only in a DDP mode; a column address control unit configured to rep... | 02/10/2009 |
| 7440349 | Integrated semiconductor memory with determination of a chip temperature An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performin... | 10/21/2008 |
| 7433229 | Flash memory device with shunt A shunt activation signal is transmitted by an external control terminal through an external transmission interface to switch a flash memory controller in a shunt mode. The shunt activation signal of the external transmission interface can set up a switch as shunt. ... | 10/07/2008 |
| 7420830 | Memory card module A memory card module includes a first circuit board, and a second circuit board. On one surface of the first circuit board, there are flash memories and a controller. The second circuit board is installed at one end of the first circuit board and is electrically con... | 09/02/2008 |
| 7411806 | Memory module and memory system A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and t... | 08/12/2008 |
| 7411794 | Carrier unit for a semiconductor device and semiconductor socket using the same In a carrier unit, a posture-stabilizing member 30 for stabilizing a bare chip to be generally parallel to a flat surface of an electrode sheet 32 is placed on the electrode sheet 32 in a carrier unit 21. ... | 08/12/2008 |
| 7408798 | 3-dimensional integrated circuit architecture, structure and method for fabrication thereof An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently opt... | 08/05/2008 |
| 7405993 | Control component for controlling a semiconductor memory component in a semiconductor memory module A semiconductor memory module includes a control component connected via various buses to semiconductor memory components on the top and bottom of a module board. Depending on the storage capacity and the rank configuration of the semiconductor memory module, addres... | 07/29/2008 |
| 7403409 | 276-pin buffered memory module with enhanced fault tolerance A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a... | 07/22/2008 |
| 7394713 | Fuse memory cell with improved protection against unauthorized access A memory device is provided, the memory device having a memory cell, a programming unit for programming the memory cell, and a switching unit for optionally connecting or isolating a terminal of the memory cell to or from a potential which serves for altering an ele... | 07/01/2008 |
| 7391635 | Method and apparatus for variable-resolution memory An apparatus and method for storage and retrieval of memory content including a storage structure containing a plurality of memory elements addressable as a two-dimensional array of memory content values, a reading circuit capable of retrieving the memory content va... | 06/24/2008 |
| 7379316 | Methods and apparatus of stacking DRAMs Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards. ... | 05/27/2008 |
| 7379334 | Memory card, semiconductor device, and method of controlling memory card A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes... | 05/27/2008 |
| 7372761 | Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used The object is to avoid an erroneous operation during a term in which an initialization is performed when a command is input. After a power source is turned on, a low level of a power-on-reset signal PWONRSTn is output until it reaches a power-on detect level.... | 05/13/2008 |
| 7367826 | Compound connector for two different types of electronic packages Disclosed is a smart card connector for transmitting signals between a smart card and an external electronic system, wherein the smart card has contacts on one of two major surfaces thereof, the connector comprising: guiding structure defining a storage space having... | 05/06/2008 |
| 7369851 | Communications network capable of determining SIM card changes in electronic devices A communication network comprising a carrier network with a service coordinator is capable of acting upon SIM card change information detected by an agent located in the electronic devices used in the communication network. In general, the agent in electronic device... | 05/06/2008 |
| 7370166 | Secure portable storage device In one embodiment of the present invention, a secure storage system includes a removable storage device having a secure storage area for storage of secure data and a public storage area and device port for coupling the removable storage device to a host, the removab... | 05/06/2008 |
| 7370168 | Memory card conforming to a multiple operation standards The invention intends to provide a memory card conforming to an HS-MMC mode in a standard of a multimedia card, while securing compatibility of both standards of the multimedia card and an SD card. In a normal MMC mode, the data is outputted at a fall edge of a cloc... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7367027 | System for generating efficient and compact update packages A system for generating efficient and compact update packages makes it possible to process a source binary image of software/firmware for an electronic device and a target binary image in order to generate a compact update package. It generates bubbles information t... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7366125 | Extensible satellite communication system A satellite network [100] includes backbone satellites [110]. The backbone satellites [110] act as routers for data units transmitted through network [100]. The backbone satellites [110] communicate with one another through inter-s... | 04/29/2008 |
