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| Number | Title | Issue Date |
| 8189358 | Semiconductor device having multiport memory A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed in a matrix s... | 05/29/2012 |
| 8179707 | Semiconductor memory devices and methods of arranging memory cell arrays thereof Semiconductor memory devices with a memory cell array including a first word line and a second word line arranged in a first direction, a source line arranged in the first direction between the first word line and the second word line, a bit line pair including a fi... | 05/15/2012 |
| 8174858 | Techniques for implementing accurate device parameters stored in a database Systems, memory modules and methods of configuring systems including memory modules are provided. The memory modules include device parameters specifically corresponding to memory devices of the memory module. The device parameters may be retrieved from a database, ... | 05/08/2012 |
| 8169809 | Tree-structure memory device A tree-structure memory device including a plurality of bit lines formed on a substrate and arranged in at least one plane substantially parallel to a substrate surface and extending substantially in a first direction, a plurality of layers having a plurality of mem... | 05/01/2012 |
| 8169838 | Memory device, control method for the same, control program for the same, memory card, circuit board and electronic equipment A memory device includes a single or a plurality of memory chips. In the memory device (memory module), the single memory chip or each of the plurality of memory chips has a memory part storing control data such as specification data and function data, and control d... | 05/01/2012 |
| 8164935 | Memory modules and methods for modifying memory subsystem performance Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge conne... | 04/24/2012 |
| 8159853 | Memory module cutting off DM pad leakage current A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit ... | 04/17/2012 |
| 8159852 | Semiconductor memory device A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor... | 04/17/2012 |
| 8154901 | Circuit providing load isolation and noise reduction Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory de... | 04/10/2012 |
| 8149606 | Semiconductor memory device A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines parallele... | 04/03/2012 |
| 8144494 | Resistance change memory device A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configur... | 03/27/2012 |
| 8139386 | Memory, computing system and method for checkpointing Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal operation. The checkpoint memory may be coupled to the processor through a peripheral bus or a memory bus. The c... | 03/20/2012 |
| 8134852 | Bridge device architecture for connecting discrete memory devices to a system A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at ... | 03/13/2012 |
| 8130526 | Programming a microchip ID register A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packag... | 03/06/2012 |
| 8130527 | Stacked device identification assignment Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an ... | 03/06/2012 |
| 8130528 | Memory system with sectional data lines A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements... | 03/06/2012 |
| 8125812 | Method and device for transmitting outgoing useful signals and an outgoing clock signal Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form... | 02/28/2012 |
| 8120938 | Method and apparatus for arranging multiple processors on a semiconductor chip A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix c... | 02/21/2012 |
| 8116109 | Low-cost high-density rectifier matrix memory A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected betwe... | 02/14/2012 |
| 8111534 | Rank select using a global select pin Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of ... | 02/07/2012 |
| 8107270 | Three dimensional hexagonal matrix memory array A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithogra... | 01/31/2012 |
| 8102689 | Semiconductor memory device having dummy sense amplifiers and methods of utilizing the same A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting ... | 01/24/2012 |
| 8102688 | Semiconductor memory devices with interface chips having memory chips stacked thereon A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respect... | 01/24/2012 |
| 8094477 | Resistance change semiconductor storage device A semiconductor storage device includes a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistan... | 01/10/2012 |
| 8081525 | Memory device including combination SRAM-ROM cells and SRAM cells alternately arranged and semiconductor device including the memory device A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell an... | 12/20/2011 |
| 8077530 | Semiconductor memory device A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit h... | 12/13/2011 |
| 8064236 | Memory module, method for using same and memory system In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an... | 11/22/2011 |
| 8054664 | Memory module and layout method therefor The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on th... | 11/08/2011 |
| 8054665 | Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a ... | 11/08/2011 |
| 8054663 | Process variation compensated multi-chip memory package A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path ... | 11/08/2011 |
| 8050071 | Memory core and semiconductor memory device having the same A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a... | 11/01/2011 |
| 8045355 | Semiconductor memory device including a reference cell A semiconductor memory device comprises a plurality of cell arrays, each cell array including a plurality of mutually parallel word lines, a plurality of mutually parallel bit lines disposed to cross these word lines, and a plurality of cells connected to the inters... | 10/25/2011 |
| 8040709 | Semiconductor storage device A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resista... | 10/18/2011 |
| 8036010 | Semiconductor memory device A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines parallele... | 10/11/2011 |
| 8031504 | Motherboard and memory device thereof A memory device can be directly mounted on a motherboard supporting DDR3 SDRAM, and then the memory device have advantages of the fly-by bus topology and the T branch topology established by the joint electron device engineering council (JEDEC). Thus, the system per... | 10/04/2011 |
| 8031505 | Stacked memory module and system A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased cap... | 10/04/2011 |
| 8023303 | Semiconductor memory device and memory access method A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input o... | 09/20/2011 |
| 8023302 | Memory device and semiconductor device It is an object of the present invention to provide an involatile memory device, in which additional writing of data is possible other than in manufacturing steps and forgery and the like due to rewriting can be prevented, and a semiconductor device having the memor... | 09/20/2011 |
| 8018752 | Configurable bandwidth memory devices and methods Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and me... | 09/13/2011 |
| 8004869 | Memory circuit arrangement and method for the production thereof A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that ... | 08/23/2011 |
