Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 8174857 | Efficient readout schemes for analog memory cell devices using multiple read threshold sets A method for data readout includes storing two or more candidate sets of read thresholds for reading from a memory device that includes a plurality of analog memory cells. A group of the memory cells from which data is to be read is identified. An order is defined a... | 05/08/2012 |
| 8149605 | Compact and accurate analog memory for CMOS imaging pixel detectors An analog memory circuit, i.e. a sample and hold circuit, wherein the source and the gate of the switching transistor is maintained at a same potential prior and after the sampling process using a transistor circuitry. The analog memory circuit comprises a memory ca... | 04/03/2012 |
| 7924587 | Programming of analog memory cells using a single programming pulse per state transition A method for data storage in analog memory cells includes defining multiple programming states for storing data in the analog memory cells. The programming states represent respective combinations of more than one bit and correspond to respective, different levels o... | 04/12/2011 |
| 7894225 | Switched current memory cell A switched current memory cell includes a current source 100 having one end connected to an operation power source (Vdd) stage, a current memory circuit unit 200 that stores an input current; which is inputted in a sampling mode of the current from the... | 02/22/2011 |
| 7589988 | Fast analog sampler for continuous recording and read-out and digital conversion system An analog sampler for continuous recording and read-out of analog data carried by a bus comprises an array of recording cells aranged in L rows and C columns. Each cell has an analog input coupled to the write bus and an analog output coupled to a read bus. The cell... | 09/15/2009 |
| 7542319 | Chalcogenide glass constant current device, and its method of fabrication and operation The invention is related to methods and apparatus for providing a two-terminal constant current device, and its operation thereof. The invention provides a constant current device that maintains a constant current over an applied voltage range of at least approximat... | 06/02/2009 |
| 7471535 | Programable identification circuitry An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate other integrated circuit devices. The integrated circuit register can also be reset to reflect the original... | 12/30/2008 |
| 7466575 | Memory device programming using combined shaping and linear spreading A method for data storage includes accepting data for storage in a memory (28) that includes multiple analog memory cells (32). The data is converted to input values. The input values are filtered using a non-linear filtering operation to produce respe... | 12/16/2008 |
| 7417881 | Low power content addressable memory A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled ... | 08/26/2008 |
| 7369600 | Burst communications apparatus and method using tapped delay lines A communications apparatus and method use tapped delay lines as multiplexers and demultiplexers. In one embodiment, a receiver (100) uses a tapped delay line (110) as a demultiplexer to acquire a burst communication at very high data rates in the range... | 05/06/2008 |
| 7363176 | Operating voltage determination for an integrated circuit Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series... | 04/22/2008 |
| 7339342 | Stepper motor controlling apparatus and pen recorder A stepper motor controlling apparatus has a driver which drives a stepper motor in response to an input pulse signal, a PWM controlling section which changes a duty ratio of the pulse signal fed to the driver to control a rotation of the stepper motor, a pulse encod... | 03/04/2008 |
| 7330798 | Operating voltage determination for an integrated circuit Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series... | 02/12/2008 |
| 7330373 | Program time adjustment as function of program voltage for improved programming speed in memory system In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the requi... | 02/12/2008 |
| 7327608 | Program time adjustment as function of program voltage for improved programming speed in programming method In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the requi... | 02/05/2008 |
| 7327604 | Clock synchronized non-volatile memory device A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives comm... | 02/05/2008 |
| 7324375 | Multi-bits storage memory A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives comm... | 01/29/2008 |
| 7321735 | Optical down-converter using universal frequency translation technology A method and system for converting an optical signal to electrical information signals, including demodulated baseband information signals and modulated baseband signals at multiple harmonics. In an embodiment, the optical information signal is amplitude modulated w... | 01/22/2008 |
| 7315267 | Mixed-mode semiconductor memory A mixed-mode semiconductor memory includes a memory bank array, an analog/digital converter, a digital/analog converter, a plurality of digital buses and a control unit. The memory bank array includes a plurality of memory banks that are each composed of a plurality... | 01/01/2008 |
| 7301836 | Feature control circuitry for testing integrated circuits An integrated circuit is provided that includes testing circuitry for testing input-output circuits. The integrated circuit contains input-output circuits that each have associated input-output pins and input and output buffers. Each input-output circuit has associa... | 11/27/2007 |
| 7295826 | Integrated frequency translation and selectivity with gain control functionality, and applications thereof Methods and apparatuses for frequency selectivity and frequency translation, and applications for such methods and apparatuses, are described herein. The method includes steps of filtering an input signal, and down-converting the filtered input signal. The filtering... | 11/13/2007 |
| 7292835 | Wireless and wired cable modem applications of universal frequency translation technology Frequency translation and applications of same are described herein, including cable modem applications. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and fil... | 11/06/2007 |
| 7292491 | Method and apparatus for controlling refresh operations in a dynamic memory device A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for... | 11/06/2007 |
| 7286397 | Clock synchronized nonvolatile memory device A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives comm... | 10/23/2007 |
| 7286414 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 10/23/2007 |
| 7286387 | Reducing the effect of write disturbs in polymer memories The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its pola... | 10/23/2007 |
| 7283397 | Flash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. A chunk of user data is programmed into a group of memory cells in parallel, the programming of individual memory cells being... | 10/16/2007 |
| 7280408 | Bitline governed approach for programming non-volatile memory In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit th... | 10/09/2007 |
| 7275190 | Memory block quality identification in a memory device If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect. This indication is stored in the memory device. In one embodiment, the quality indication is stored in a pr... | 09/25/2007 |
| 7272678 | DSP bus monitoring apparatus and method A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external... | 09/18/2007 |
| 7272758 | Defective memory block identification in a memory device During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller... | 09/18/2007 |
| 7268809 | Analog buffer memory for high-speed digital image capture A digital imaging system uses a high density, high speed analog/multi-level memory to temporarily store image data at high rates for extended periods of time. A portion of the stored data is transmitted for image processing and compression. When image processing and... | 09/11/2007 |
| 7259981 | Nonvolatile analog memory A nonvolatile analog memory uses pairs of ferroelectric field effect transistors (FFETs). Each pair is defined by a first FFET and a second FFET. When an analog value is to be stored in one of the pairs, the first FFET has a saturation voltage applied thereto, and t... | 08/21/2007 |
| 7242382 | Display device having reduced number of signal lines A display device includes a display unit which displays an image, memories which store information regarding control of the display unit, an operation circuit unit which controls the display unit to display the image based on the information stored in the memories, ... | 07/10/2007 |
| 7239771 | Method and system for controlling an optical switch using dynamic compensation A free space optical switch that uses both an open loop control mode and a closed loop control mode. The open loop control mode is used to transition to a state where at least some light is sensed at a destination port. A closed loop control mode is then used, where... | 07/03/2007 |
| 7221596 | pFET nonvolatile memory A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine a cell state. The gate of the RT provides for charge/in... | 05/22/2007 |
| 7221574 | Semiconductor storage device A semiconductor storage device has a memory cell (501, 502) storing data; bit lines (BL1, BL2) connected to the memory cell, allowing therethrough data input or output to or from the memory cell; a sense amplifier (506a) connected ... | 05/22/2007 |
| 7221017 | Memory utilizing oxide-conductor nanolaminates Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A float... | 05/22/2007 |
| 7221586 | Memory utilizing oxide nanolaminates Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region b... | 05/22/2007 |
| 7218150 | Semiconductor integrated circuit device and differential small-amplitude data transmission apparatus An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance ... | 05/15/2007 |