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| Number | Title | Issue Date |
| 7830743 | Sequential access memory method A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory arr... | 11/09/2010 |
| 7791979 | Semiconductor memory device When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 ... | 09/07/2010 |
| 7697372 | Access to printing material container The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the storage device of the invention, an ID comparator determines whether or ... | 04/13/2010 |
| 7609567 | System and method for simulating an aspect of a memory circuit A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the sys... | 10/27/2009 |
| 7599247 | Memory and method of writing data Semiconductor memory devices 10 are each furnished with a memory array 100 having an EEPROM array 101 and a mask ROM array 102. Identifying information for identifying each semiconductor memory device 10 is stored at the beginning ... | 10/06/2009 |
| 7573779 | Semiconductor memory and electronic device A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for turning on/off power corresponding to row addresses of the memory ce... | 08/11/2009 |
| 7564739 | Storage cell design evaluation circuit including a wordline timing and cell access detection circuit A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same l... | 07/21/2009 |
| 7522470 | Semiconductor memory device When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 ... | 04/21/2009 |
| 7499372 | Semiconductor memory device When writing 16-bit write data to the memory array 100 which can store data of 8 bits per 1 row, the semiconductor memory device 10 first writes the upper 8 bits to the 1st write restricted row of the memory array 100. The increment controller | 03/03/2009 |
| 7477570 | Sequential access memory with system and method A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory arr... | 01/13/2009 |
| 7466623 | Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof A pseudo SRAM which can perform read and write operations of data in a continuous burst mode in such a manner that it continuously generates burst row and column address signals, which gradually rise, based on external address signals that have already been received... | 12/16/2008 |
| 7433260 | Memory device and print recording material receptacle providing memory device The operation code decoder 204 having received an access enable signal EN acquires and decodes the command, and sends the decoded command to the read/write controller 206. In the event that the received command is a write command, the read/write contro... | 10/07/2008 |
| 7428178 | Memory circuit containing a chain of stages A memory circuit is provided that includes at least one chain of at least three stages each having a data input, a data output, and a control signal input. Each of the stages between the first stage and the last stage includes a first NMOS transistor having a gate c... | 09/23/2008 |
| 7397727 | Write burst stop function in low power DDR sDRAM A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is common in a low power double data rate (DDR) dynamic random access memory (DRAM) device. In the memory device,... | 07/08/2008 |
| 7394710 | Auto-recovery fault tolerant memory synchronization Automatic fault recovery of upsets in a memory controller are provided to minimize data loss. In addition to memory control, the present invention allows for the incorporation of majority voting circuits with integrated alignment between three voted data streams. Th... | 07/01/2008 |
| 7394718 | Semiconductor memory device having a global data bus There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can be not occurred, or can be minimized upon an issuance thereof. Furth... | 07/01/2008 |
| 7391672 | Sequential memory and accessing method thereof A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are eq... | 06/24/2008 |
| 7388799 | Semiconductor memory device A semiconductor memory device for consuming a uniform amount of current includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for outputting a refresh address, having a plurality of bits, correspond... | 06/17/2008 |
| 7355917 | Two-dimensional data memory A two-dimensional data memory (1) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the column direction are coupled locally to their respectively adjac... | 04/08/2008 |
| 7353356 | High speed, low current consumption FIFO circuit A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of input data, and outputs a write counter value. The memory circuit stores ... | 04/01/2008 |
| 7349246 | Initial firing method and phase change memory device for performing firing effectively In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and ... | 03/25/2008 |
| 7349277 | Method and system for reducing the peak current in refreshing dynamic random access memory devices A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset co... | 03/25/2008 |
| 7327632 | Interface circuit An interface apparatus having a first and a second buffer storage unit, the first buffer storage unit being associated with a first domain and the second buffer storage unit being associated with a second domain, and the buffer storage units being connected to one a... | 02/05/2008 |
| 7315479 | Redundant memory incorporating serially-connected relief information storage A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in seri... | 01/01/2008 |
| 7304899 | Integrated semiconductor memory An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the progr... | 12/04/2007 |
| 7266028 | Method and apparatus for bit mapping memories in programmable logic device integrated circuits during at-speed testing Programmable logic devices may use shadow memory for gathering diagnostic information while testing memory blocks. Memory block testing may be performed at any clock speed allowed during normal operation in a system such as the highest allowed clock speed. Built in ... | 09/04/2007 |
| 7263014 | Semiconductor memory device having N-bit prefetch type and method of transferring data thereof A semiconductor memory device in which only global I/O buses, which receive one or more data groups that must be output first among a N number of data groups that are prefetched in a N-bit prefetch type, from an array of memory cells are precharged with a ½ power s... | 08/28/2007 |
| 7254090 | Semiconductor memory device An internal address generating circuit sequentially generates internal addresses in the burst read operation, with an external address being set as an initial value. A memory core has plural memory cells and sequentially outputs, in response to activation of a colum... | 08/07/2007 |
| 7254055 | Initial firing method and phase change memory device for performing firing effectively In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and ... | 08/07/2007 |
| 7254076 | Semiconductor memory device for improving response margin of redundancy flag signal and redundancy driving method for the same A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving method is improved by sensing generation of an internal address corresp... | 08/07/2007 |
| 7251249 | Integrated high speed switch router using a multiport architecture A switch/router circuit integrates a multi-port memory array with the Media Access Control (MAC) units to facilitate direct transfer of packet payloads to the destination port. The store and forward functions are performed using a single memory cell with multiple pa... | 07/31/2007 |
| 7239573 | Method of storing data in blocks per operation The present invention is to provide a method of storing data for driving an MMC or SD under an operating system (e.g., Linux), which comprises the steps of collecting data in a plurality of discreet blocks of a high-speed buffer for each writing request made by a de... | 07/03/2007 |
| 7236407 | Flash memory architecture for optimizing performance of memory having multi-level memory cells A flash memory device having a pipelined RAS/CAS architecture is logically organized as an array of rows and columns of multi-bit flash memory cells each capable of being selectively programmed to have a threshold voltage corresponding to one of a plurality of multi... | 06/26/2007 |
| 7227805 | Semiconductor memory device having a global data bus There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can be not occurred, or can be minimized upon an issuance thereof. Furth... | 06/05/2007 |
| 7221609 | Fine granularity DRAM refresh A method, device, and system are included. In one embodiment, the method included issuing a single row refresh command for a first row in a memory starting at a target address, incrementing a row counter, continuing issuing a single row refresh command for each subs... | 05/22/2007 |
| 7215580 | Non-volatile memory control According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed... | 05/08/2007 |
| 7215561 | Semiconductor memory system having multiple system data buses The semiconductor memory system includes a memory controller, N system data buses, and first through P-th memory module groups. The N system data buses are connected to the memory controller and respectively have a width of M/N bits. The first through P-th memory mo... | 05/08/2007 |
| 7196962 | Packet addressing programmable dual port memory devices and related methods In a packet addressing method, one or more memory blocks are selected from a plurality of memory blocks and one or more data I/O pads are selected from a plurality of data I/O pads via which data input or output to/from the selected memory blocks are loaded, memory ... | 03/27/2007 |
| 7196968 | Method of driving data lines, and display device and liquid crystal display device using method A method of driving source lines is arranged as follows: One output signal line S61 of a source driver is connected to a plurality of lines corresponding to respective source lines SR7 through SB12, and these source lines from SR7 (starti... | 03/27/2007 |
| 7190614 | Operation scheme for programming charge trapping non-volatile memory A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash. The method includes determining a data value from one of more than two data values to be stored in the memory cell, and applying a gate voltage... | 03/13/2007 |
