Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 7668039 | Address counter, semiconductor memory device having the same, and data processing system An address counter includes FIFO units and first and second command counters that control the groups. The first command counter has a first mode in which any one of input gates is conducted in response to a first internal command and a second mode in which a plurali... | 02/23/2010 |
| 7663966 | Single-clock, strobeless signaling system A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset re... | 02/16/2010 |
| 7646668 | Maintaining dynamic count of FIFO contents in multiple clock domains Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock dom... | 01/12/2010 |
| 7643373 | Driving method and system for a phase change memory An embodiment of a method for driving a phase change memory, comprising counting an access number of a phase change memory, wherein the access number is the number of times that the phase change memory has been accessed; refreshing the phase change memory when the n... | 01/05/2010 |
| 7590026 | Access to printing material container The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the storage device of the invention, an ID comparator determines whether or ... | 09/15/2009 |
| 7580322 | High speed programming for nonvolatile memory A nonvolatile memory device is programmed by selectively scanning input data bits to detect data bits to be programmed, and programming the detected data bits. The detected data bits may be programmed in predetermined units. The input data bits may be selectively sc... | 08/25/2009 |
| 7558152 | Address counter for nonvolatile memory device An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the mem... | 07/07/2009 |
| 7551514 | Semiconductor memory utilizing a method of coding data A semiconductor memory device utilizing a data coding method in an initial operation. The device includes a plurality of counters that count the number of data bits and flag information data bits. A data coding unit selectively applies a first and second operation m... | 06/23/2009 |
| 7447111 | Counter control signal generating circuit A counter control signal generating circuit is disclosed. The circuit includes a first counter configured to receive a latched external address, and count the latched external address for a first latency, thereby generating a first counted address, a second counter ... | 11/04/2008 |
| 7436718 | Semiconductor memory device including fuse detection circuit to determine successful fuse-cutting rate for optical fuse-cutting conditions A fuse detection method for reading out a program state of each fuse and generating a killer signal indicating the program state of the fuse; counting the program state indicated by the killer signal to obtain a count value; inputting an expected value for the progr... | 10/14/2008 |
| 7436725 | Data generator having stable duration from trigger arrival to data output start A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing ... | 10/14/2008 |
| 7428184 | Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency A circuit arrangement for generating an n-bit output pointer in a semiconductor memory comprises at least one m-bit interface for accepting an m-bit reference signal, at least one m-bit binary counter, a decoder arrangement connected downstream of the binary counter... | 09/23/2008 |
| 7428180 | Semiconductor memory devices and methods of testing for failed bits of semiconductor memory devices A semiconductor memory device includes a flash memory, a buffer memory configured to receive expected data for testing for failed bits in the flash memory, and a failed bit control unit configured to receive the expected data from the buffer memory, to receive read ... | 09/23/2008 |
| 7426154 | Sensor adjusting circuit A sensor adjusting circuit for adjusting a digital sensor, whose circuit scale is small and which can maintain high accuracy in a wide adjustment range is provided. A sensor adjusting circuit for adjusting an analog input signal inputted from a sensor and outputting... | 09/16/2008 |
| 7418573 | Address generation apparatus and operation apparatus An address generation apparatus and an operation apparatus are shown to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An address generation apparatus has at least one counter setting a count val... | 08/26/2008 |
| 7400531 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The accumulating counter accumulates and stores a number of program loops... | 07/15/2008 |
| 7397707 | Compressed event counting technique and application to a flash memory system A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. Complementary embo... | 07/08/2008 |
| 7397711 | Distributed write data drivers for burst access memories An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating ... | 07/08/2008 |
| 7394710 | Auto-recovery fault tolerant memory synchronization Automatic fault recovery of upsets in a memory controller are provided to minimize data loss. In addition to memory control, the present invention allows for the incorporation of majority voting circuits with integrated alignment between three voted data streams. Th... | 07/01/2008 |
| 7372717 | Methods for resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage su... | 05/13/2008 |
| 7372768 | Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of... | 05/13/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7369432 | Method for implementing a counter in a memory with increased memory efficiency A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the fir... | 05/06/2008 |
| RE40252 | Flash memory control method, flash memory system using the control method and flash memory device using the control method A method of correcting errors of a flash memory comprises steps of modifying the data of a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein, checking for the presence or absence of an err... | 04/22/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7355921 | Device in a memory circuit for definition of waiting times A device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is sw... | 04/08/2008 |
| 7355911 | Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories) A semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories is disclosed. In one embodiment, in order to test the semiconductor memory components, test data are written to the memory ... | 04/08/2008 |
| 7355922 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and ... | 04/08/2008 |
| 7352642 | Semiconductor memory device A semiconductor memory device includes a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region; word lines; a counter cell array including counter cells provided to correspond to the word line... | 04/01/2008 |
| 7352606 | Monotonic counter using memory cells A monotonous counter formed as an integrated circuit, each counting bit being provided by a memory cell containing at least one memorization element formed of a polysilicon resistor, programmable by irreversible decrease in its value. ... | 04/01/2008 |
| 7353357 | Apparatus and method for pipelined memory operations A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory ... | 04/01/2008 |
| 7349279 | Memory Device Having a Configurable Oscillator for Refresh Operation A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency f... | 03/25/2008 |
| 7349289 | Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an inp... | 03/25/2008 |
| 7345950 | Synchronous semiconductor memory device A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency set... | 03/18/2008 |
| 7342841 | Method, apparatus, and system for active refresh management A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus r... | 03/11/2008 |
| 7342835 | Memory device with pre-fetch circuit and pre-fetch method A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense amplifiers are coupled to each memory block to at least one of read da... | 03/11/2008 |
| 7334093 | Block programmable priority encoder in a CAM A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical... | 02/19/2008 |
| 7330951 | Apparatus and method for pipelined memory operations A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and... | 02/12/2008 |
| 7330381 | Method and apparatus for a continuous read command in an extended memory array The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocate... | 02/12/2008 |
| 7330929 | CAM modified to be used for statistic calculation in network switches and routers A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM device, the matching entry's counter may be incremented. Alternatively, if... | 02/12/2008 |