Class 365/231 - Using selective matrix

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter where at least a single matrix is used to
No. of patents: 84
Last issue date: 12/14/2010

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Number	Title	Issue Date
7852705	Method of and circuit for configuring a plurality of memory elements A method of configuring a plurality of memory elements having selectable dimensions, the method comprising the steps of selecting a width of a data word to be output by a circuit having the plurality of memory elements; selecting a width for memory locations of the ...	12/14/2010
7715271	Using dedicated read output path to reduce unregistered read access time for a FPGA embedded memory A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory arr...	05/11/2010
7414916	Using dedicated read output path to reduce unregistered read access time for FPGA embedded memory A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory arr...	08/19/2008
7388802	Memory protected against attacks by error injection in memory cells selection signals A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstruct...	06/17/2008
7362909	Coding device and method and decoding device and method The present invention makes it possible to effectively encode/decode position information of leaves or nodes in tree-structured information by using a less amount of bits. The coding device according to the present invention includes a branching layer discriminating...	04/22/2008
7349267	Semiconductor memory device In a memory cell array, source lines are provided so that each of the source lines is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a gro...	03/25/2008
7336547	Memory device having conditioning output data A memory device has a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data. During a memory operation, the memory device transfers both of the condition data and the memory data to...	02/26/2008
7266036	Semiconductor memory device A semiconductor memory device is provided with a plurality of memory blocks including a plurality of word lines and a plurality of bit line pairs intersecting the individual word lines, a plurality of memory cells provided at each of intersections where the individu...	09/04/2007
7209376	Stacked semiconductor memory device A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell ...	04/24/2007
7106639	Defect management enabled PIRM and method A defect management enabled PIRM including a data storage medium providing a plurality of cross point data storage arrays. Each array provides a plurality of memory cells. The arrays are allocated into separate super arrays, the separate super arrays virtually align...	09/12/2006
7003622	Semiconductor memory A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the regular RAM can be replaced, and a control block for selecting either at ...	02/21/2006
6996662	Content addressable memory array having flexible priority support A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal...	02/07/2006
6982920	Flash array implementation with local and global bit lines A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a contr...	01/03/2006
6975553	Nonaligned access to random access memory Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offse...	12/13/2005
6958745	Display device, method for driving the same, and portable terminal apparatus using the same A selection-addressing-type liquid crystal display selectively addresses a signal line of a pixel unit using groups of three selectors of a selector circuit in a time-division manner. A level converter level shifts selector pulses having a voltage swing correspondin...	10/25/2005
6940780	Flash array implementation with local and global bit lines A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a contr...	09/06/2005
6909636	Flash array implementation with local and global bit lines A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a contr...	06/21/2005
6862243	Flash array implementation with local and global bit lines A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a contr...	03/01/2005
6839266	Memory module with offset data lines and bit line swizzle configuration A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected t...	01/04/2005
6768663	Semiconductor device array having dense memory cell array and hierarchical bit line scheme A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204	07/27/2004
6667894	Acquisition process by analog signal sampling, and an acquisition system to implement such a process An acquisition process for signal sampling includes high-speed analog signal sampling, storing the samples of the analog signal in a matrix of memory cells, and re-reading the samples from the cells at low speed. Two identical memory devices are provided ...	12/23/2003
6636454	Low-power consumption semiconductor memory device A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. I...	10/21/2003
6567340	Memory storage cell based array of counters A multi-counter based system having a counter array. Each counter of the array having a memory cell. The system also includes an address decoder coupled to the counter array to select at least one of the memory cells within the counter array and read/writ...	05/20/2003
6507534	Column decoder circuit for page reading of a semiconductor memory A column decoder circuit for page reading of a semiconductor memory includes a first level decoder stage, a second level decoder stage, and a plurality of bit selection stages, each comprising a plurality of selection branches; wherein each selection bran...	01/14/2003
6473339	Redundancy architecture for an interleaved memory A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of pack...	10/29/2002
6434433	External components for a microprocessor system for control of plural control elements and operating method The external intelligent component (3) connected with a microprocessor system (2) is described for essentially automatic control of a control element (1) without burdening the microprocessor system operation. The control parameters for the control element...	08/13/2002
6400597	Semiconductor memory device The number of apparently independently operating memory sets can be changed by providing the same number of address setting circuits as that of memory cell arrays. Since the number of mounted address setting circuits increases compared with a case where t...	06/04/2002
6373770	Integrated circuit memory devices with configurable block decoder circuits A memory device includes a memory array and a configurable decoder circuit operatively associated with the memory array and configurable to one of a first state or a second state. In the first state, the configurable decoder circuit is operative, responsi...	04/16/2002
6363026	Address generating device for use in multi-stage channel interleaver/deinterleaver An address generating device for addressing data stored in an interleaver memory in B rows and F columns, where F is not 2k for a positive integer k. A row counter being responsive to B clock pulses, outputs carry signal when the row counter co...	03/26/2002
6262925	Semiconductor memory device with improved error correction When a cell of a memory cell array (C0 and C1) located at a position further from the word select line driver is selected, data that is read from the memory cell array (C0, C1) is sent via only sense amplifier circuits (S0, S1) to the output buffer circui...	07/17/2001
6212121	Semiconductor memory device with multiple sub-arrays of different sizes A semiconductor memory device includes a memory cell array divided into a plurality of sub-arrays. The number of memory cells per bit line in at least one of the sub-arrays differs from the number of memory cells per bit line in other sub-arrays. When the...	04/03/2001
6192000	Semiconductor memory device having decreased layout area and method of manufacturing the same A word line driving circuit drives four word lines in response to a signal supplied from a main row decoder through a main word line and in response to a word line driving voltage supplied from a sub-row decoder. When the word line driving circuit is not ...	02/20/2001
6115305	Method and apparatus for testing a video display chip A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column...	09/05/2000
6081474	Semiconductor memory In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line...	06/27/2000
5963498	Method for controlling memory address of digital signal processor Disclosed is a method for controlling a memory address of a digital signal processor in which a memory address is independently managed for each for during parallel processing of a plurality of jobs and no program of the same content as others is stored r...	10/05/1999
5943693	Algorithmic array mapping to decrease defect sensitivity of memory devices A method and apparatus for addressing a memory device are described. A first logical address is translated into a first physical address to access a first storage location at a first row and a first column in an array of memory cells. A second logical add...	08/24/1999
5930790	String-match array for substitutional compression A circuit for implementing a substitutional compressor. Comparators compare a current input pixel against a large number of previous pixels, the "history", stored in a series of shift registers. Each register and associated comparator constitutes a cell. ...	07/27/1999
5910928	Memory interface unit, shared memory switch system and associated method A memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible master data path for the transfer data to or from th...	06/08/1999
5732041	Memory interface unit, shared memory switch system and associated method A memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible a master data path for the transfer data to or from ...	03/24/1998
5612925	Semiconductor memory device A semiconductor memory device, including a memory cell array having a plurality of memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals. The device includes a control unit which receives ...	03/18/1997

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Class 365/231 - Using selective matrix