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| Number | Title | Issue Date |
| 7983111 | Memory controller for controlling memory and method of controlling memory A memory controller for controlling a memory that operates in synchronization with a clock signal, wherein the memory sequentially outputs data of addresses starting from a target address in synchronization with the clock signal after receiving a read command and th... | 07/19/2011 |
| 7952956 | Variable resistance memory device and system A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the... | 05/31/2011 |
| 7773453 | FIFO peek access Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after... | 08/10/2010 |
| 7558148 | Memory controller A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus... | 07/07/2009 |
| 7495993 | Onboard data storage and method A semiconductor memory device and an associated method suitable for use in specific applications with predictable memory access pattern, such as in a capsule camera. The memory device takes advantage of the memory access pattern to simplify address processing circui... | 02/24/2009 |
| 7436689 | Non-volatile semiconductor memory When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and ... | 10/14/2008 |
| 7433258 | Posted precharge and multiple open-page RAM architecture A method and architecture that overcomes the problem of latency-caused performance degradation of electronic memory systems. The method involves a “Posted Precharge,” by which an external command for Precharge is given as early as possible, such as immediately f... | 10/07/2008 |
| 7372755 | On-chip storage memory for storing variable data bits An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data bits, a wrapper for converting the memory into a first-in first-out ... | 05/13/2008 |
| 7352648 | Semiconductor memory At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction. The incomplete cell array is disposed closer to a signal control unit... | 04/01/2008 |
| 7353357 | Apparatus and method for pipelined memory operations A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory ... | 04/01/2008 |
| 7330951 | Apparatus and method for pipelined memory operations A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and... | 02/12/2008 |
| 7319634 | Address converter semiconductor device and semiconductor memory device having the same An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity sele... | 01/15/2008 |
| 7281030 | Method of reading a remote memory In an example embodiment, a method of reading data from a remote device transfers data directly from the remote memory of the remote device to the local memory of the local device. A message is sent from the local device to the remote device which includes a transpo... | 10/09/2007 |
| 7272066 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 09/18/2007 |
| 7266020 | Method and apparatus for address and data line usage in a multiple context programmable logic device A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the ro... | 09/04/2007 |
| 7266038 | Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units (101a-101n), a select signal generating unit (105) for generating a sel... | 09/04/2007 |
| 7254690 | Pipelined semiconductor memories and systems The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or... | 08/07/2007 |
| 7239573 | Method of storing data in blocks per operation The present invention is to provide a method of storing data for driving an MMC or SD under an operating system (e.g., Linux), which comprises the steps of collecting data in a plurality of discreet blocks of a high-speed buffer for each writing request made by a de... | 07/03/2007 |
| 7212448 | Method and apparatus for multiple context and high reliability operation of programmable logic devices A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the ro... | 05/01/2007 |
| 7193928 | Signal output device and method for the same A signal output device includes a first selection unit operable to select a plurality of signal lines from a signal line group, a second selection unit operable to select a reference clock of signals carried by the selected signal lines, a determination unit operabl... | 03/20/2007 |
| 7177782 | Methods and arrangements for capturing runtime information Methods and arrangements for capturing information related to operational conditions are disclosed. Embodiments include volatile memory to quickly record operational parameters via, e.g., basic input output system (BIOS) code, system management interrupt (SMI) code ... | 02/13/2007 |
| 7167404 | Method and device for testing configuration memory cells in programmable logic devices (PLDS) A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage devi... | 01/23/2007 |
| 7148826 | Data input circuit and semiconductor device utilizing data input circuit A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input ser... | 12/12/2006 |
| 7142476 | Refresh counter circuit and control method for refresh operation A refresh counter circuit generating a row address during refresh operation for the memory device which has a normal area for storing data bits and a parity area for storing parity bits, including; n-stage counter which generates the row address corresponding to an ... | 11/28/2006 |
| 7124256 | Memory device for burst or pipelined operation with mode selection circuitry An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device wi... | 10/17/2006 |
| 7120078 | Synchronous semiconductor memory In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command ... | 10/10/2006 |
| 7117335 | Method of and apparatus for controlling of regulating industrial processes A method of controlling an industrial process by a programmable process control has the steps of taking data in form of resulting values which are decisive for the process, storing the data in a storage of a programmable process control, during starting a control pr... | 10/03/2006 |
| 7116602 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 10/03/2006 |
| 7103742 | Burst/pipelined edo memory device An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device wi... | 09/05/2006 |
| 7099229 | Nonvolatile memory device having circuit for stably supplying desired current during data writing A memory block is divided into block units for which parallel data write is performed. Current supply sections capable of supplying a power supply voltage and a ground voltage are provided for block units, independently of one another. With this configuration, in ea... | 08/29/2006 |
| 7099179 | Conductive memory array having page mode and burst mode write capability Conductive memory array having page mode and burst mode write capability. The conductive memory array includes two-terminal memory plugs and driver circuits configured to write information to the memory plugs in two cycles. The array also includes associated circuit... | 08/29/2006 |
| 7093066 | Method for bus capacitance reduction Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits. ... | 08/15/2006 |
| 7088625 | Distributed write data drivers for burst access memories An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating ... | 08/08/2006 |
| 7085193 | Clock-synchronous semiconductor memory device A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal af... | 08/01/2006 |
| 7085906 | Memory device A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer ci... | 08/01/2006 |
| 7075857 | Distributed write data drivers for burst access memories An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitio... | 07/11/2006 |
| 7072923 | Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern e... | 07/04/2006 |
| 7057946 | Semiconductor integrated circuit having latching means capable of scanning Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent regist... | 06/06/2006 |
| 7054218 | Serial memory address decoding scheme A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for accessing the memory. A pulse generator supplies an appropriate number of ... | 05/30/2006 |
| 7042795 | Flash memory device with burst read mode of operation A flash memory device is disclosed that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are c... | 05/09/2006 |
