Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 8179739 | Semiconductor device and its manufacturing method A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a selec... | 05/15/2012 |
| 8164973 | Storage apparatus and method of controlling storage apparatus A storage apparatus includes: a plurality of storage sections each of which corresponds to each of a plurality of addresses; a read pointer register that outputs a read pointer indicating an address of a storage section from which data is read; a write pointer regis... | 04/24/2012 |
| 8164971 | Dual power rail word line driver and dual power rail word line driver array A dual power rail word line driver for driving a word line of a memory array according to a predecode signal from a decoder powered by a first supply voltage is provided. A signal buffering unit is coupled between the word line and a node. A pull-down unit is couple... | 04/24/2012 |
| 8159899 | Wordline driver for memory Subject matter disclosed herein relates to accessing memory, and more particularly to a wordline driver of same. ... | 04/17/2012 |
| 8154945 | Decoding circuit withstanding high voltage via low-voltage MOS transistor and the implementing method thereof The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected ... | 04/10/2012 |
| 8154946 | Data storage device A device to selectively activate memory chips includes a memory unit including n memory chips activated in response to n memory chip activation signals (n is a natural number), a controller to generate m control signals (m is a natural number), and a memory chip act... | 04/10/2012 |
| 8154947 | Multi-column addressing mode memory system including an integrated circuit memory device A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of ... | 04/10/2012 |
| 8144541 | Method and apparatus for adjusting and obtaining a reference voltage A method for adjusting a reference voltage is provided, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the actual reference voltage with a benchmark value to obtain a deviation... | 03/27/2012 |
| 8139437 | Wordline driving circuit of semiconductor memory device Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation a... | 03/20/2012 |
| 8130588 | Semiconductor memory device having power saving mode A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by decoding a received row address and being synchronized with an inter... | 03/06/2012 |
| 8130589 | Semiconductor memory device using only single-channel transistor to apply voltage to selected word line A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to... | 03/06/2012 |
| 8120987 | Structure and method for decoding read data-bus with column-steering redundancy A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one memory cell in the array and is capable of executing column steering redun... | 02/21/2012 |
| 8116165 | Memory with improved data reliability An integrated circuit is provided including at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory c... | 02/14/2012 |
| 8116150 | Resistance change memory with current control and voltage control during a write operation, and write method of the same A resistance change memory includes a resistance change element having a high-resistance state and a low-resistance state in accordance with write information, and a write circuit configured to supply a write current that the write current flowing through the resist... | 02/14/2012 |
| 8107311 | Software programmable multiple function integrated circuit module An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable func... | 01/31/2012 |
| 8107312 | Memory chip array Example embodiments are directed to a memory chip array including a plurality of cell arrays and at least one predecoder commonly connected to the plurality of cell arrays, wherein the memory chip array promotes an efficient arrangement structure of the memory chip ... | 01/31/2012 |
| 8107313 | Semiconductor memory and memory system A plurality of cell arrays are assigned different addresses. An access information unit holds access enable information indicating the number of the cell arrays to be simultaneously activated. An array control unit activates at least one of the cell arrays correspon... | 01/31/2012 |
| 8102728 | Cache optimizations using multiple threshold voltage transistors In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a s... | 01/24/2012 |
| 8102729 | Resistive memory device capable of compensating for variations of bit line resistances A variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory c... | 01/24/2012 |
| 8089823 | Processor instruction cache with dual-read modes A processor including a memory and a control module. The memory has an array of cells. The control module is configured to: determine a number of access cycles along a first word line; determine an extended period based on the number of the access cycles; generate a... | 01/03/2012 |
| 8085616 | Block decoder of a flash memory device A block decoder increases the integration level of a flash memory device by reducing the number of control signals. Address signals are substituted with existing high voltage switch signals. The block decoder of a flash memory device includes a primary decoding unit... | 12/27/2011 |
| 8085615 | Multi-state resistance changing memory with a word line driver for applying a same program voltage to the word line A resistance changing memory unit cell includes a current control component operably coupled to a bit sense line, and a resistance changing memory element coupled between the current control component and a word line. ... | 12/27/2011 |
| 8081535 | Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices a... | 12/20/2011 |
| 8081536 | Circuit for memory module A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory circuits activated by a first number of chip-select signals. The circ... | 12/20/2011 |
| 8081534 | Automatic scrambling of input/output data according to row addresses in a semiconductor memory device A semiconductor memory device is capable of scrambling input/output data according to row addresses. The semiconductor memory device includes a local line driving block configured to differentially drive a positive local line and a negative local line by selectively... | 12/20/2011 |
| 8081537 | Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices a... | 12/20/2011 |
| 8072834 | Line driver circuit and method with standby mode of operation A line driver circuit can include an integrated circuit substrate of a first conductivity type having at least a first and a second well of a second conductivity type formed therein. The second well can be coupled to a first power supply node. A first transistor can... | 12/06/2011 |
| 8072835 | Row address decoder and semiconductor memory device having the same A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fo... | 12/06/2011 |
| 8072837 | Circuit providing load isolation and memory domain translation for memory module A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in r... | 12/06/2011 |
| 8072836 | Systems, methods and devices for arbitrating die stack position in a multi-die stack device Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked dies are arbitrated to select one of the dies as the primary die and the other as secondary. Each die incl... | 12/06/2011 |
| 8068382 | Semiconductor memory with multiple wordline selection A semiconductor memory circuit, comprising: a memory array, the memory array including a plurality of wordlines each connected to a respective row of cells and a plurality of bitlines each connected to a respective column of cells. The semiconductor memory circuit a... | 11/29/2011 |
| 8068381 | Cache memory Disclosed is a cache memory, and more particularly to a cache memory, in which a word-line voltage control logic unit and a word-line driver are added as a logic circuit between a row decoder and a word line, so that a reinforcement voltage signal having a higher le... | 11/29/2011 |
| 8059483 | Address receiving circuit for a semiconductor apparatus An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the s... | 11/15/2011 |
| 8050134 | Multi-column addressing mode memory system including an integrated circuit memory device A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of ... | 11/01/2011 |
| 8050133 | Word line driver, method for driving the word line driver, and semiconductor memory device having the word line driver A word line driver, a method for driving the word line driver, and a semiconductor memory device having the word line driver. The word line driver receives a main word line driving signal and a sub word line driving signal, to drive a word line with a word line driv... | 11/01/2011 |
| 8040751 | Semiconductor memory device A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for hold... | 10/18/2011 |
| 8027218 | Processor instruction cache with dual-read modes A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a firs... | 09/27/2011 |
| 8027219 | Semiconductor memory devices having signal delay controller and methods performed therein A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a r... | 09/27/2011 |
| 8014226 | Integrated circuit memory with word line driving helper circuits An integrated circuit memory 2 incorporates a first array of bit cells 4 and a second array of bit cells 6 with word line driver circuitry 8 disposed therebetween. Word line helper circuitry 18, 20 is disposed at the opposite edges... | 09/06/2011 |
| 8009505 | Semiconductor memory device A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a contro... | 08/30/2011 |
