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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Number | Title | Issue Date |
| 8144540 | Two-port 8T SRAM design An integrated circuit includes a two-port static random access memory (SRAM) cell, which includes a first half write-port, a second half write-port, and a read-port. The first half write-port includes a first pull-up transistor, a first pull-down transistor, and a f... | 03/27/2012 |
| 8130587 | Efficient method of replicate memory data with virtual port solution A hardware arrangement for a memory bitcell, including a primary decoder for decoding a common memory address portion among a plurality of memory addresses, and a plurality of secondary decoders each for decoding an uncommon memory address portion of each of the plu... | 03/06/2012 |
| 8120986 | Multi-port semiconductor memory device having variable access paths and method therefor A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit t... | 02/21/2012 |
| 8111579 | Circuits and methods for reducing minimum supply for register file cells A register file employing a shared supply structure to improve the minimum supply voltage. ... | 02/07/2012 |
| 8102727 | Semiconductor memory device A semiconductor memory device comprises a memory cell array including a plurality of mutually intersecting word lines and bit lines, and a plurality of memory cells connected at intersections thereof and each having a read port and a write port provided independentl... | 01/24/2012 |
| 8098540 | Dynamic power saving memory architecture A memory includes multiple interface ports. The memory also includes at least two sub-arrays each having an instance of all of the bit lines of the memory and a portion of the word lines of the memory. The memory has a common decoder coupled to the sub-arrays and co... | 01/17/2012 |
| 8072833 | Semiconductor memory device A semiconductor memory device includes a first write bit line, a second write bit line, a write word line, a first read bit line, a read word line, and a memory cell array including a plurality of memory cells, and arranged the plurality of memory cells in a matrix ... | 12/06/2011 |
| 8072818 | Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a pl... | 12/06/2011 |
| 8050116 | Memory cell write Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a wri... | 11/01/2011 |
| 8050132 | Semiconductor device A semiconductor device 110 has a plurality of memory cell blocks provided with a plurality of memory cells storing a predetermined amount of data. Each memory cell block has four or more inputs and outputs, and is internally provided with a read address decod... | 11/01/2011 |
| 8031552 | Multi-port memory device with serial input/output interface A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode regi... | 10/04/2011 |
| 8018790 | Serial memory interface A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configu... | 09/13/2011 |
| 7986582 | Method of operating a memory apparatus, memory device and memory apparatus A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank in... | 07/26/2011 |
| 7961547 | Memory device using a common write word line and a common read bit line A one read/two write SRAM circuit of which memory cell size is small, and high-speed operation is possible. The SRAM circuit includes first and second flip-flop circuits which are connected in parallel to a common write word line; a first write control circuit which... | 06/14/2011 |
| 7940599 | Dual port memory device A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first b... | 05/10/2011 |
| 7907469 | Multi-port memory device for buffering between hosts and non-volatile memory devices A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A vol... | 03/15/2011 |
| 7907468 | Memory device having data paths permitting array/port consolidation and swapping Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of... | 03/15/2011 |
| 7903497 | Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding ... | 03/08/2011 |
| 7898894 | Static random access memory (SRAM) cells The present invention provides an improved SRAM cell. Specifically, the present invention provides an SRAM cell having one or more sets of stacked transistors for isolating the cell during a read operation. Depending on the embodiment, the SRAM cell of the present i... | 03/01/2011 |
| 7898895 | Semiconductor device A semiconductor device of the invention comprises: a memory cell array including memory cells formed at intersections between word lines and bit lines; first and second input/output ports each defined for inputting/outputting data of the memory cell array; sense amp... | 03/01/2011 |
| 7898896 | Semiconductor device The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a s... | 03/01/2011 |
| 7894296 | Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N... | 02/22/2011 |
| 7889576 | Semiconductor storage device This invention provides static random access memory (SRAM). The SRAM has a plurality of memory cells arranged in row and column directions. The plurality of memory cells each have a latch circuit in which input and output terminals of a pair of inverters are cross-c... | 02/15/2011 |
| 7885139 | Multi-chip package A multi-chip package includes a plurality of memory chips and a control chip, wherein the control chip stores information about whether the memory chips are operating normally and selects chips that are operating normally according to an address signal. ... | 02/08/2011 |
| 7885138 | Three dimensional twisted bitline architecture for multi-port memory Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical po... | 02/08/2011 |
| 7843758 | Multi-chip package flash memory device and method for reading status data therefrom A method for reading status data from a multi-chip memory device including pluralities of memory chips is comprised of: providing a command to request an output of the status data to the plurality of memory chips; and accepting the status data of the plurality of me... | 11/30/2010 |
| 7839713 | Reading and writing data to a memory cell in one clock cycle A memory circuit, where data is read from and written to the memory cell in one clock cycle via a port without pre-charging the port between reading data from and writing data to the memory cell via the port in the one clock cycle, is described. In one aspect, an em... | 11/23/2010 |
| 7835219 | Multi-port memory device A multi-port memory device including a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes a phase locked loop (PLL) unit for generating an internal clock signa... | 11/16/2010 |
| 7817492 | Memory device using SRAM circuit A one read/two write SRAM circuit of which memory cell size is small, and high-speed operation is possible. The SRAM circuit includes first and second flip-flop circuits which are connected in parallel to a common write word line; a first write control circuit which... | 10/19/2010 |
| 7813213 | Pulsed arbitration system A pulsed arbitration without coincidence detection system has a pulsed arbitration circuit that is controlled by an internal write pulse and a block/group row access and that has an output coupled to a sub-word line. A sub-word line area contains the pulsed arbitrat... | 10/12/2010 |
| 7778105 | Memory with write port configured for double pump write A memory with a write port configured for double-pump writes. The memory includes a first and second memory locations each having one or more bit cells, and one or more bit lines each coupled to corresponding ones of the bit cells. A write port is coupled to each of... | 08/17/2010 |
| 7773450 | Integrated circuit having a word line driver An integrated circuit having a plurality of sectors is disclosed. One embodiment includes a sector driver for simultaneously driving word lines corresponding to a single sector, the sector driver being connected to each word line and comprising a programmable sector... | 08/10/2010 |
| 7738312 | Semiconductor memory device One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the se... | 06/15/2010 |
| RE41325 | Dual port random-access-memory circuitry Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator tra... | 05/11/2010 |
| 7715269 | Semiconductor memory device and semiconductor device comprising the same A semiconductor memory device includes a plurality of input/output (I/O) ports, a plurality of memory cell arrays and a region configurator. The region configurator is adapted to hold share region information about at least one share region. In the memory cell array... | 05/11/2010 |
| 7710814 | Fast read port for register file Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneo... | 05/04/2010 |
| 7710815 | Access unit for a static random access memory An access unit for a static random access memory (SRAM) is provided. The access unit comprises two inverters. Two different variable voltages are supplied to the two inverters via bitlines to cause an imbalance in the current strengths between the two inverters so t... | 05/04/2010 |
| 7701800 | Multi-port memory device with serial input/output interface A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode regi... | 04/20/2010 |
| 7697362 | Arbitration for memory device with commands A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS an... | 04/13/2010 |
| 7697363 | Memory device having data input and output ports and memory module and memory system including the same A memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between ... | 04/13/2010 |
