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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 7974145 | Semiconductor memory device using bus inversion scheme A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion s... | 07/05/2011 |
| 7656738 | Nonvolatile semiconductor storage device having a low resistance write-bit-line and a low capacitance read-bit-line pair A memory cell array includes memory cells disposed in a matrix. A plurality of word-lines are arranged in the memory cell array to select a memory cell in a row direction. A read bit-line pair is arranged in a direction perpendicular to the word-line to read data fr... | 02/02/2010 |
| 7554874 | Method and apparatus for mapping memory A memory mapping method is provided for writing block data composed of a plurality of lines in first and second memories, each memory including at least two banks of the same number. The method maps the memories such that continuous even-numbered lines are written i... | 06/30/2009 |
| 7551511 | NAND flash memory device and method of forming a well of a NAND flash memory device Disclosed herein are a NAND flash memory device and a method of forming a well of the NAND flash memory device. Triple wells of a NAND flash memory device are formed within a cell region in plural. A cell block including flash memory cells is formed on the triple we... | 06/23/2009 |
| 7525867 | Storage circuit and method therefor Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (1... | 04/28/2009 |
| 7453758 | Control system for a dynamic random access memory and method of operation thereof A dynamic random access memory device includes an array of dynamic random access memory cells subdivided into a group of blocks. Each of the blocks of memory cells can be independently operated in either a single cell mode or a twin cell mode. ... | 11/18/2008 |
| 7420874 | Integrated circuit memory device, system and method having interleaved row and column control An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second c... | 09/02/2008 |
| 7417899 | Method of verifying flash memory device A method of verifying a flash memory device includes discharging memory cell strings respectively connected to an even bit line and an odd bit line. Next, a voltage is applied to the memory cell strings respectively connected to the even bit line and the odd bit lin... | 08/26/2008 |
| 7411858 | Dual-plane type flash memory device having random program function and program operation method thereof A dual-plane type flash memory device having a random program function and program operation method thereof. The flash memory device includes a first plane, a second plane, a first X-decoder, and a second X-decoder. The first plane includes first memory blocks seque... | 08/12/2008 |
| 7382670 | Semiconductor integrated circuit device There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the t... | 06/03/2008 |
| 7376021 | Data output circuit and method in DDR synchronous semiconductor device Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted ... | 05/20/2008 |
| 7376026 | Integrated semiconductor memory having sense amplifiers selectively activated at different timing An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and second sense amplifiers are arranged on a left-hand side of the memory cell array. Due to “post-sense cou... | 05/20/2008 |
| 7373491 | Processor with versatile external memory interface A processor architecture suitable for embedded systems and compatible with different kinds of external memory, executes a bootstrap program to determine the characteristics of the external memory before connection with the external memory. For this purpose, system s... | 05/13/2008 |
| 7369444 | Early read after write operation memory device, system and method A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write da... | 05/06/2008 |
| 7362619 | Data strobe synchronization circuit and method for double data rate, multi-bit writes A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates... | 04/22/2008 |
| 7362650 | Memory arrangement having a plurality of RAM chips Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing... | 04/22/2008 |
| 7362640 | Apparatus and method for self-refreshing dynamic random access memory cells A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the mai... | 04/22/2008 |
| 7353308 | Avoiding oscillation in self-synchronous bi-directional communication system In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to... | 04/01/2008 |
| 7349289 | Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an inp... | 03/25/2008 |
| 7350044 | Data move method and apparatus An improved Flash memory device, control circuit, or data handling methods is described that facilitate the moving and consolidating data in split and non-split user/overhead data sector architectures, moving and storing user and overhead data from and to separate n... | 03/25/2008 |
| 7340560 | Methods and devices for accessing a memory using multiple separate address mapped temporary storage areas A method of accessing an integrated circuit memory device can include reading from an address in a first memory sub-block during a first clock cycle. The address of a first data memory block address mapped to the first memory sub-block can be written to during the f... | 03/04/2008 |
| 7324564 | Transmitting odd-sized packets over a double data rate link A method may involve: receiving an even number of odd-sized packets for transmission over a double data rate link; re-packetizing the even number of odd-sized packets into several even-sized packets; transmitting the even-sized packets over the double data rate link... | 01/29/2008 |
| 7321949 | Memory device including self-ID information Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each ba... | 01/22/2008 |
| 7319606 | Memory A memory capable of effectively reducing the chip size not only by sharing a read/write circuit but also by reducing a memory cell size is provided. This memory comprises a first memory cell array having a plurality of first memory cells, a second memory cell array ... | 01/15/2008 |
| 7319622 | Bitline shielding for thyristor-based memory Method and apparatus for writing and reading information to and from a memory cell. For a read, a write path is used to electrically shield at least one adjacent bitline from a bitline associated with the memory cell to be read, and the memory cell is read while the... | 01/15/2008 |
| 7317656 | Semi-conductor memory component, and a process for operating a semi-conductor memory component The invention relates to a semi-conductor memory component and process for operating a semi-conductor memory component, including activating the memory cells of a memory cell array, when one or several memory cell(s) included in the first set of memory cells need(s)... | 01/08/2008 |
| 7310258 | Memory chip architecture with high speed operation A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at lea... | 12/18/2007 |
| 7302505 | Receiver multi-protocol interface and applications thereof A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a second formatted input signal to produce an amplified input signal. The... | 11/27/2007 |
| 7297996 | Semiconductor memory device for storing data in memory cells as complementary information A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plur... | 11/20/2007 |
| 7295466 | Use of recovery transistors during write operations to prevent disturbance of unselected cells A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array has a plurality of memory cells, each of which i... | 11/13/2007 |
| 7289373 | High performance memory device A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected ... | 10/30/2007 |
| 7290118 | Address control system for a memory storage device A memory storage device having an address control system is disclosed. The memory storage device includes memory cells and an address control system configured to decode a bit number which identifies a number of the memory cells which are selected in parallel. The m... | 10/30/2007 |
| 7290098 | Method and apparatus for interleaving data streams In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data. ... | 10/30/2007 |
| 7283409 | Data monitoring for single event upset in a programmable logic device Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators... | 10/16/2007 |
| 7277340 | Smart memory read out for power saving A method and a circuit are given, to implement and realize power saving Sense Electronics Endowed (SEE) memory using modified memory read cycles, named as Smart Memory Readout (SMR). In an SMR-mode read cycle, the memory is only active a small fraction of a clock cy... | 10/02/2007 |
| 7277334 | Method and apparatus for synchronization of row and column access operations A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising... | 10/02/2007 |
| 7274617 | Non-volatile semiconductor memory A non-volatile semiconductor memory includes: a cell array including a plurality of memory cells arranged in a matrix; a plurality of bit lines extending in a column direction of the matrix; a sense amplifier configured to amplify data read out from the memory cells... | 09/25/2007 |
| 7269087 | Semiconductor memory device In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connect... | 09/11/2007 |
| 7269090 | Memory access with consecutive addresses corresponding to different rows A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decodin... | 09/11/2007 |
| 7266651 | Method for in-place memory interleaving and de-interleaving A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address ... | 09/04/2007 |
