Class 365/230.02 - Multiplexing

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter which includes the transmission of plural
No. of patents: 745
Last issue date: 02/07/2012

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Number	Title	Issue Date
8111578	Memory devices having redundant arrays for repair Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes a first number of columns of memory cells, and one or more global input/output (I/O) lines shared by the ...	02/07/2012
7936634	Memory control circuit and memory accessing method A control circuit applied in a memory that comprises a first memory block and a second memory block, and each of the first and the second memory blocks includes a boundary cell. The control circuit comprises an address decoder, a first Y-multiplexer, and a second Y-...	05/03/2011
7885136	Semiconductor memory device having high stability and quality of readout operation A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge se...	02/08/2011
7817491	Bank control device and semiconductor device including the same A semiconductor memory device includes a plurality of banks a plurality of banks stacked in a column direction, a global data line corresponding to the plurality of banks and a common global data line driving unit for multiplexing data on a plurality of local data l...	10/19/2010
7813215	Circuit and method for generating data output control signal for semiconductor integrated circuit The data output control signal generating circuit includes a delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output ena...	10/12/2010
7701799	Semiconductor device A semiconductor device may include a decoder for decoding a plurality of internal command signals and outputting a first Y-address enabling signal; a Y-address enabling signal generator for receiving the first Y-address enabling signal and outputting a second Y-addr...	04/20/2010
7684278	Method and apparatus for implementing FIFOs using time-multiplexed memory in an integrated circuit Method and apparatus for implementing first-in-first-out (FIFO) memories using time-multiplexed memory in an integrated circuit are described. A block random access memory (BRAM) circuit embedded in the integrated circuit is provided. The BRAM includes at least one ...	03/23/2010
7643370	Memory device having conditioning output data Some embodiments of the invention include a memory device having a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data. During a memory operation, the memory device transfers both...	01/05/2010
7643371	Address/data multiplexed device A semiconductor device and a method of controlling the semiconductor device, the semiconductor device including: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the...	01/05/2010
7570542	Circuit and method for generating data output control signal for semiconductor integrated circuit The data output control signal generating circuit includes a delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output ena...	08/04/2009
7564733	Memory device and method having programmable address configurations A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, addr...	07/21/2009
7502276	Method and apparatus for multi-word write in domino read SRAMs A domino read SRAM capable of writing multiple wordlines simultaneously. A read/write multiplexer may allow conventional, single-wordline selection during a read operation, while allowing external logic, such as an ABIST controller, to enable multiple wordlines duri...	03/10/2009
7489583	Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire c...	02/10/2009
7480201	Daisy chainable memory chip A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip. If...	01/20/2009
7471573	Integrated circuit device and electronic instrument An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wor...	12/30/2008
7463544	Device programmable to operate as a multiplexer, demultiplexer, or memory device A device that is programmable to operate as a memory device, a multiplexer, or a demultiplexer includes: a first column decoder; a memory array coupled to the first column decoder; a plurality of selectors coupled to the memory array; and a second column decoder cou...	12/09/2008
7443744	Method for reducing wiring and required number of redundant elements A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent...	10/28/2008
7440335	Contention-free hierarchical bit line in embedded memory and method thereof A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower leve...	10/21/2008
7436726	Circuit for and method of reading data in an asynchronous FIFO including a backup address circuit for re-reading data A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write addres...	10/14/2008
7436688	Priority encoder circuit and method A priority encoder circuit can include a number of sectional encoder circuits that each encode “m” inputs signals into sets of “P” encoder outputs, where m>p. Each sectional encoder circuit can also output a group indication signal representing the activatio...	10/14/2008
7430137	Non-volatile memory cells in a field programmable gate array A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel...	09/30/2008
7426607	Memory system and method of operating memory system A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the m...	09/16/2008
7414916	Using dedicated read output path to reduce unregistered read access time for FPGA embedded memory A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory arr...	08/19/2008
7411862	Control signal training A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase w...	08/12/2008
7405993	Control component for controlling a semiconductor memory component in a semiconductor memory module A semiconductor memory module includes a control component connected via various buses to semiconductor memory components on the top and bottom of a module board. Depending on the storage capacity and the rank configuration of the semiconductor memory module, addres...	07/29/2008
7405992	Method and apparatus for communicating command and address signals Apparatus and methods for communicating command and address inputs to a memory device. In one embodiment, a memory device includes a shared bus interface defined by a portion of pins from a command bus interface and a portion of pins from an address bus interface. E...	07/29/2008
7405980	Shared terminal memory interface A memory architecture for a disk drive system in which Synchronous Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two me...	07/29/2008
7400548	Method for providing multiple reads/writes using a 2read/2write register file array Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into...	07/15/2008
7394716	Bank availability indications for memory device and method therefor In one arrangement, a memory device (100) can include a number of banks (102-0 to 102-2n) and corresponding counters (104-0 to 104-2n). In response to a corresponding active access ...	07/01/2008
7391632	Apparatus of selectively performing fast hadamard transform and fast fourier transform, and CCK modulation and demodulation apparatus using the same A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complex...	06/24/2008
7391636	Semiconductor memory device and arrangement method thereof A semiconductor memory device and an arrangement method thereof are included. The semiconductor memory device includes column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word line...	06/24/2008
7388802	Memory protected against attacks by error injection in memory cells selection signals A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstruct...	06/17/2008
7376021	Data output circuit and method in DDR synchronous semiconductor device Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted ...	05/20/2008
7372768	Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of...	05/13/2008
7369904	Integration method for automation components A method for integrating a number of automation components into an industrial controller with a uniform running level model of the runtime system. The basic clock of the running level model is devised from either an internal timer, an internal clock of a communicati...	05/06/2008
7370134	System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl...	05/06/2008
7366864	Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t...	04/29/2008
7366031	Memory arrangement and method for addressing a memory A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to the leaves of the binary tree. ...	04/29/2008
7362651	Using common mode differential data signals of DDR2 SDRAM for control signal transmission A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core hav...	04/22/2008
7362641	Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo...	04/22/2008

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Class 365/230.02 - Multiplexing