Class 365/230.01 - ADDRESSING

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter including selection of a memory location.
No. of patents: 1086
Last issue date: 01/17/2012

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Number	Title	Issue Date
8098539	Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of ...	01/17/2012
8050130	Semiconductor memory device and internal data transmission method thereof In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receiv...	11/01/2011
8004925	Variable resistive memory A variable resistive memory device includes memory sectors, memory cells in each of the memory sectors, sub-wordlines including a first in signal communication with at least a first pair of the memory cells in a first sector and a second in signal communication with...	08/23/2011
7952952	Reduction of fusible links and associated circuitry on memory dies The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number o...	05/31/2011
7859937	Apparatus and method for controlling write access to a group of storage elements An apparatus and method for controlling write access to a group of storage elements is provided. Each storage element within the group is identified by an n-bit address, and the total number of storage elements in the group is less than 2n. Write enable c...	12/28/2010
7839712	Semiconductor memory arrangement A semiconductor memory arrangement includes a substrate, a first control device disposed on the substrate and adapted to receive command and address signals, a second control device, and a plurality of memory units. The second control device is adapted to receive th...	11/23/2010
7830740	Semiconductor memory device having selectable transfer modes A semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/outp...	11/09/2010
7826299	Method and apparatus for operating maskable memory cells A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask...	11/02/2010
7652903	Hit ahead hierarchical scalable priority encoding logic and circuits In this invention a hit ahead multi-level hierarchical scalable priority encoding logic and circuits are disclosed. The advantage of hierarchical priority encoding is to improve the speed and simplify the circuit implementation and make circuit design flexible and s...	01/26/2010
7636271	User selectable banks for DRAM A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. M...	12/22/2009
7606110	Memory module, memory unit, and hub with non-periodic clock and methods of using the same A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality o...	10/20/2009
7593270	Integrated circuit device and electronic instrument An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines. The display memory includes a plurality of RAM blocks, each of the RAM blocks i...	09/22/2009
7558144	Circuit for controlling pulse width of auto-refresh signal and circuit for generating internal row address for auto refresh A circuit for controlling a pulse width of a refresh signal is provided. The circuit includes a first pulse width controller for receiving a first refresh signal having a first enable period, and generating a second refresh signal having a second refresh signal, and...	07/07/2009
7450461	Semiconductor memory device and transmission/reception system provided with the same In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related ci...	11/11/2008
7437527	Memory device with delayed issuance of internal write command A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation...	10/14/2008
7417908	Semiconductor storage device In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memor...	08/26/2008
7417881	Low power content addressable memory A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled ...	08/26/2008
7414874	Semiconductor memory device Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region al...	08/19/2008
7414912	Semiconductor flash memory A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read me...	08/19/2008
7414914	Semiconductor memory device A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for hold...	08/19/2008
7403447	Method for stabilizing electronic circuit operation and electronic apparatus using the same An operation signal generator circuits are provided to continue to operate an object circuit which is not operated unless an operation signal arrives for the purpose of power consumption reduction, and thereby the object circuit is put into dummy operation. This ena...	07/22/2008
7397713	Flash EEprom system A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Sele...	07/08/2008
7394716	Bank availability indications for memory device and method therefor In one arrangement, a memory device (100) can include a number of banks (102-0 to 102-2n) and corresponding counters (104-0 to 104-2n). In response to a corresponding active access ...	07/01/2008
7392343	Memory card having a storage cell and method of controlling the same A controller comprises a host interface section and a processing circuit. The host interface section receives a command sequence outputted from a host apparatus to a first nonvolatile semiconductor memory. The processing circuit processes the command sequence output...	06/24/2008
7388802	Memory protected against attacks by error injection in memory cells selection signals A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstruct...	06/17/2008
7388801	Reduction of fusible links and associated circuitry on memory dies The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number o...	06/17/2008
RE40356	Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells locate...	06/03/2008
7383416	Method for setting a second rank address from a first rank address in a memory module A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first r...	06/03/2008
7379357	Semiconductor memory device having advanced repair circuit A semiconductor device for comparing an input address with a repair address includes a signal controller for generating control signals. An address latch unit in response to the control signals latches the address. Each of N number of M-bit address comparators compa...	05/27/2008
7379379	Storage device employing a flash memory A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the ...	05/27/2008
7372768	Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of...	05/13/2008
7363465	Semiconductor device, microcomputer, and electronic equipment A semiconductor device comprising a bus master and a bus slave connected by a second bus is provided. A bus control unit (BCU) comprises a first relative address control circuit that performs a process for requesting the access using a relative address to a semicond...	04/22/2008
7362641	Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo...	04/22/2008
7359264	Semiconductor memory device A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant e...	04/15/2008
7359268	Semiconductor memory device for low voltage A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data from the global data line to the local data line pair; and an input/o...	04/15/2008
7359273	Semiconductor memory device having layout for minimizing area of sense amplifier region and word line driver region A semiconductor memory device has a layout that minimizes the area required for sense amplifier and word line driver regions. In the semiconductor memory device of the present invention, decoding drivers are arranged in sense amplifier regions. Further, the wiring f...	04/15/2008
7355895	Nonvolatile semiconductor memory and driving method the same A nonvolatile semiconductor memory includes a memory cell array, a control circuit and an address control circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix of rows and columns. The control circuit sets a write/erase mode in resp...	04/08/2008
7355231	Memory circuitry with oxygen diffusion barrier layer received over a well base A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semic...	04/08/2008
7353401	Device and method for data protection by scrambling address lines A device and method for data protection by scrambling address lines is disclosed, which includes a redundancy area-setting unit, a redundancy area-mapping rule unit, an area check unit, an address-mapping unit and a multiplexer. The area check unit compares an addre...	04/01/2008
7350016	High speed DRAM cache architecture A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memor...	03/25/2008

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Class 365/230.01 - ADDRESSING