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| Number | Title | Issue Date |
| 8139436 | Integrated circuits, systems, and methods for reducing leakage currents in a retention mode An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coup... | 03/20/2012 |
| 8085614 | Source control circuit and semiconductor memory device using the same A source control circuit comprises a control signal generating unit for generating a standby signal which is enabled in a standby condition, and a switching unit connected between a power line for supplying power to an internal circuit and an external power and cont... | 12/27/2011 |
| 8068377 | Semiconductor memory device to reduce off-current in standby mode A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to... | 11/29/2011 |
| 8068378 | Clock and power fault detection for memory modules A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupl... | 11/29/2011 |
| 8009502 | Systems, methods and devices for power control in mass storage devices Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, an energy storage circuit is powered using a variable voltage controlled to limit the current draw from a power supply, ... | 08/30/2011 |
| 8004924 | Voltage regulator for memory A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage differen... | 08/23/2011 |
| 7990797 | State of health monitored flash backed dram module A device includes: non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to move data from a volatile memory to the non-volatile memory upon a loss of power of a primary power source of the volatile mem... | 08/02/2011 |
| 7974144 | Memory with tunable sleep diodes A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device. ... | 07/05/2011 |
| 7903495 | Selectively controlled memory Embodiments of methods, apparatuses, and systems that enable power conservation in data buffering components are disclosed. Other embodiments may also be disclosed. ... | 03/08/2011 |
| 7894291 | Circuit and method for controlling a standby voltage level of a memory A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable... | 02/22/2011 |
| 7894292 | Semiconductor device for preventing erroneous write to memory cell in switching operational mode between normal mode and standby mode When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply ... | 02/22/2011 |
| 7839717 | Semiconductor device with reduced standby failures A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and... | 11/23/2010 |
| 7826298 | Semiconductor memory device with low standby current In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power ... | 11/02/2010 |
| 7808856 | Method to reduce leakage of a SRAM-array A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire ... | 10/05/2010 |
| 7751270 | Memory device with reduced standby power consumption and method for operating same Disclosed herein are memory devices comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, and methods of operating said memory devices, the methods comprising: (a) determining an actual value o... | 07/06/2010 |
| 7729193 | Backup for volatile state retention in the absence of primary circuit power A backup volatile state retention circuit is provided with low leakage current for employment with a volatile memory circuit to store the value of the latter during power down of the volatile circuit or during power-down or inactivation of neighboring or peripheral ... | 06/01/2010 |
| 7729194 | Backup for circuits having volatile states An electrical circuit contains volatile states that are lost without continued application of power to circuit elements to preserve their volatile states. A first power source in the circuit provides power to the volatile state circuit for holding and preserving the... | 06/01/2010 |
| 7724604 | Clock and power fault detection for memory modules A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupl... | 05/25/2010 |
| 7623405 | SRAM with switchable power supply sets of voltages A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of th... | 11/24/2009 |
| 7619947 | Integrated circuit having a supply voltage controller capable of floating a variable supply voltage An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to output at least one variable supply voltage to at least one supply terminal of the integrated circuit The con... | 11/17/2009 |
| 7548482 | Memory device for early stabilizing power level after deep power down mode exit A memory device for early stabilization and rapid increase of a power level after deep power down exit includes a deep power down exit pulse generator, a deep power down exit mode signal generator, a current driving unit, a controller and a voltage generator. The de... | 06/16/2009 |
| 7525865 | Control circuit for refreshing voltages in a non-volatile memory during a standby mode and a method thereof Disclosed is a method for refreshing voltages in a non volatile memory during a standby mode. The method comprises generating a first node voltage and a second node voltage through a resistance ladder, storing the voltages in a pair of capacitors, comparing the volt... | 04/28/2009 |
| 7518940 | Control circuit for stable exit from power-down mode A power-down mode exit control circuit enables a memory device to exit from an initially set power-down mode state using a clock enable signal. Specifically, although a clock enable signal is inputted in an unstable state at an initial operation indicating that a su... | 04/14/2009 |
| 7443758 | Circuit and method of generating high voltage for programming operation of flash memory device Provided is a high voltage generator for a flash memory device including a voltage pumping unit configured to generate a high voltage in response to a pumping clock signal, a transistor having a gate coupled to the high voltage and a source coupled to a program volt... | 10/28/2008 |
| 7430676 | Method and apparatus for changing the clock frequency of a memory system One embodiment of the present invention provides a system that facilitates changing a clock frequency in a memory system. During operation, the system receives a command to change the clock frequency to a new clock frequency. The system then iteratively changes the ... | 09/30/2008 |
| 7430148 | Volatile memory elements with boosted output voltages for programmable logic device integrated circuits Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with conf... | 09/30/2008 |
| 7430149 | Semiconductor device There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by a... | 09/30/2008 |
| 7428649 | Power supply delivery for leakage suppression modes Circuitry gates the power supply to limit standby power in an integrated circuit. The IR drop through clamps may be compensated using a regulator feedback signal to improve the power performance and allow the power supply regulator to supply the best quality power s... | 09/23/2008 |
| 7420857 | Semiconductor integrated circuit and leak current reducing method The present invention provides a semiconductor integrated circuit device which includes at least an SRAM memory cell array comprising a plurality of memory cells each constituted of a circuit including load MOS transistors, drive MOS transistors and transfer MOS tra... | 09/02/2008 |
| 7414897 | Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage... | 08/19/2008 |
| 7414898 | Semiconductor memory device with internal power supply Provided is a semiconductor memory device including an internal power supply with low current consumption, which includes: an active interval security block for generating active interval security signals with operation intervals by a row active signal and a column ... | 08/19/2008 |
| 7414911 | Cascade wake-up circuit preventing power noise in memory device A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in t... | 08/19/2008 |
| 7411855 | Semiconductor device with improved power supply arrangement A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both ... | 08/12/2008 |
| 7408829 | Methods and arrangements for enhancing power management systems in integrated circuits Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternat... | 08/05/2008 |
| 7408816 | Memory voltage generating circuit A memory voltage generating circuit includes a first control module, a core circuit, and a second control module. The core circuit includes a regulation amplifier, a first MOSFET, a second MOSFET, and a switch. An output terminal and an inverting input terminal of t... | 08/05/2008 |
| 7405991 | Semiconductor device voltage supply for a system with at least two, especially stacked, semiconductor devices The invention is directed to a system and method comprising a first semiconductor device and a second semiconductor device, wherein the first semiconductor device comprises a voltage supply means, characterized in that the voltage supply means of the first semicondu... | 07/29/2008 |
| 7404093 | System and method for saving and restoring a processor state without executing any instructions from a first instruction set A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program executio... | 07/22/2008 |
| 7400547 | Semiconductor integrated circuit with power-reducing standby state A semiconductor integrated circuit has a sense amplifier which senses and outputs data read out from memory cells connected to word lines and bit lines, and a read-out control circuit which has a standby state consuming minimum necessary power and a read state readi... | 07/15/2008 |
| 7397708 | Technique to suppress leakage current Embodiments of the invention generally provide a method and wordline driver having a reduced leakage current. In one embodiment, a wordline is driven to a boosted high voltage with a driver transistor of the wordline driver if the wordline driver is in an operationa... | 07/08/2008 |
| 7397721 | Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit Embodiments of the invention provide a standby leakage current reduction circuit and a semiconductor memory device comprising the standby leakage current reduction circuit. The invention provides a circuit adapted to reduce standby leakage current in a semiconductor... | 07/08/2008 |
