Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 8111577 | System comprising a state-monitoring memory element Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses... | 02/07/2012 |
| 8085613 | Power detecting circuit, portable device and method for preventing data loss In step S508, it is determined whether or not a power low signal SRC_LOSS outputted from the data latch is change. Generally Speaking, the power low signal SRC_LOSS outputted from the data latch would be changed according to the state of the power voltage of ... | 12/27/2011 |
| 8068376 | Low leakage high stability memory array system Systems design and methods are provided for maintaining the memory array stability while reducing power consumption in the form of leakage current in a memory array. One embodiment discloses a memory array system, which comprises a plurality of memory cells, a monit... | 11/29/2011 |
| 8064275 | Local sensing and feedback for an SRAM array An integrated circuit having an SRAM array includes SRAM cells arranged in rows and columns, and a global read circuit connected to globally read SRAM cells corresponding to accessed rows and columns of the SRAM array. The SRAM array also includes a separate, local ... | 11/22/2011 |
| 8064281 | System comprising a state-monitoring memory element Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses... | 11/22/2011 |
| 8040750 | Dual mode memory system for reducing power requirements during memory backup transition A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configurat... | 10/18/2011 |
| 8031551 | Systems, methods and devices for monitoring capacitive elements in devices storing sensitive data Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data storage device stores data in response to data accesses under the control of a memory control circuit. A solid-st... | 10/04/2011 |
| 7983107 | Flash backed DRAM module with a selectable number of flash chips A memory device for use with a primary power source and a backup power source, includes: volatile memory; an interface for connecting to a backup power source; a plurality of ports, each of which is for receiving a different corresponding non-volatile memory chip; a... | 07/19/2011 |
| 7869300 | Memory device control for self-refresh mode In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the m... | 01/11/2011 |
| 7852701 | Circuits for and methods of determining a period of time during which a device was without power A circuit structure for determining a period of time during which a device was without power is disclosed. The circuit structure comprises a volatile memory storing known data and a test circuit coupled to the volatile memory, the test circuit determining an amount ... | 12/14/2010 |
| 7778101 | Memory module and method of performing the same A memory module and a method of performing the same for access of an external electronic device are provided herein. The memory module includes a NAND-type flash memory, a dynamic random access memory (DRAM) unit, and a memory controller. The dynamic random access m... | 08/17/2010 |
| 7715268 | Non-volatile storage apparatus and a control method thereof Storage apparatus can support various memory units with different standards based on the method which drives the power control-and-switch circuit in the power management unit according to a control signal caused by the ID code of a memory unit to control the second ... | 05/11/2010 |
| 7660182 | Extraction and stabilization of a binary code based on physical parameters of an integrated circuit An integrated cell for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the val... | 02/09/2010 |
| 7643369 | Information processing apparatus, memory unit erroneous write preventing method, and information processing system To make it possible to reliably halt writing processing while restraining erroneous writing to the memory unit, present apparatus has a memory unit to which data is written for each write request; a voltage converting unit which converts a first power source voltage... | 01/05/2010 |
| 7599241 | Enhanced write abort mechanism for non-volatile memory In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM ... | 10/06/2009 |
| 7558143 | Programmable logic device with power-saving architecture A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment, the PLD includes a switch such as an internal power supp... | 07/07/2009 |
| 7463543 | Lock-out device and semiconductor integrated circuit device including the same A lock-out device is provided that determines whether to lock out a chip or not according to the result of operation voltage drop detected at a plurality of positions in a semiconductor integrated circuit device. As a result, unnecessary lock-out operations can be p... | 12/09/2008 |
| 7443758 | Circuit and method of generating high voltage for programming operation of flash memory device Provided is a high voltage generator for a flash memory device including a voltage pumping unit configured to generate a high voltage in response to a pumping clock signal, a transistor having a gate coupled to the high voltage and a source coupled to a program volt... | 10/28/2008 |
| 7440352 | Semiconductor memory device capable of selectively refreshing word lines A semiconductor memory device comprises a plurality of memory cells connected to a plurality of word lines grouped in word line sets. Each of the word line sets is connected to a word line enable signal generation unit which stores information indicating whether dat... | 10/21/2008 |
| 7440354 | Memory with level shifting word line driver and method thereof A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory ... | 10/21/2008 |
| 7436732 | Internal power supply generating circuit without a dead band An internal power supply generating circuit has a control circuit for controlling a control node voltage of a driver circuit thereof. During an overdrive duration, the control node voltage is set at an appropriate level of an operation range by controlling the contr... | 10/14/2008 |
| 7430148 | Volatile memory elements with boosted output voltages for programmable logic device integrated circuits Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with conf... | 09/30/2008 |
| 7430149 | Semiconductor device There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by a... | 09/30/2008 |
| 7426136 | Non volatile memory An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed i... | 09/16/2008 |
| 7414897 | Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage... | 08/19/2008 |
| 7408829 | Methods and arrangements for enhancing power management systems in integrated circuits Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternat... | 08/05/2008 |
| 7408830 | Dynamic power supplies for semiconductor devices This invention discloses a power supply management circuit which comprises at least one switching circuit coupled between a power supply and a power recipient circuit, and at least one voltage booster circuit coupled between a control circuit and the power recipient... | 08/05/2008 |
| 7408834 | Flash controller cache architecture A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write back and read-look-ahead. Write-through and write back policies may improve spee... | 08/05/2008 |
| 7403426 | Memory with dynamically adjustable supply In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed. ... | 07/22/2008 |
| 7404093 | System and method for saving and restoring a processor state without executing any instructions from a first instruction set A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program executio... | 07/22/2008 |
| 7397719 | Volatile semiconductor memory A volatile semiconductor memory includes a self-test controller detecting a defect of a memory cell, and an address storage storing a defective address indicating an address of a defective memory cell, and a refresh adjust circuit setting a refresh cycle of a memory... | 07/08/2008 |
| 7395445 | Controller for power supplies A state machine implemented controller is provided in which a logic core 20 is reconfigurable in response to state data held within a memory 22. Thus, on transition from one state to a next state the data held within the memory 22 is used to rec... | 07/01/2008 |
| 7395466 | Method and apparatus to adjust voltage for storage location reliability According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storag... | 07/01/2008 |
| 7391658 | Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage... | 06/24/2008 |
| 7391666 | DRAM power bus control A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power ... | 06/24/2008 |
| 7390262 | Non-volatile memory storing critical data in a gaming machine A method and apparatus of dynamically storing critical data of a gaming machine by allocating and deallocating memory space in a gaming machine is disclosed. One or more embodiments describe downloading or removing a new game to a gaming machine such that all existi... | 06/24/2008 |
| 7388799 | Semiconductor memory device A semiconductor memory device for consuming a uniform amount of current includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for outputting a refresh address, having a plurality of bits, correspond... | 06/17/2008 |
| 7388800 | Memory control device having less power consumption for backup When it is detected that the voltage of a main power supply is reduced below a predetermined value during a normal operation, a power controller switches a power supply for a DRAM from the main power supply to a battery power supply and makes an instruction signal f... | 06/17/2008 |
| 7379370 | Semiconductor memory After a refresh operation, a word control circuit holds the selection state of a word line selection signal line selected in each memory block corresponding to a refresh address. Further, in response to an access request, the word control circuit unselects only a wo... | 05/27/2008 |
| 7380048 | System and method for managing data in memory for reducing power consumption A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type. ... | 05/27/2008 |
