Class 365/227 - Conservation of power

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter having means for reduction of operational
No. of patents: 1197
Last issue date: 05/22/2012

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Number	Title	Issue Date
8184498	Semiconductor memory device A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a contro...	05/22/2012
8174924	Power saving method and circuit thereof for a semiconductor memory A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost p...	05/08/2012
8174923	Voltage-stepped low-power memory device This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory ce...	05/08/2012
8154944	Semiconductor memory device Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed ...	04/10/2012
8134883	Semiconductor device A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data a...	03/13/2012
8068373	Power management of memory via wake/sleep cycles A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, the...	11/29/2011
8054709	Power control circuit and semiconductor memory device using the same A semiconductor memory device comprises a power control circuit for outputting a power voltage in a read operation period and a write operation period, and an internal circuit operating by the power voltage supplied thereto. ...	11/08/2011
8031550	Voltage regulator circuit for a memory circuit A voltage regulator circuit for a memory circuit comprises a voltage divider, a capacitor, an active-mode voltage regulator and a standby-mode voltage regulator. The active-mode voltage regulator is always on while in active mode, and turned on whenever a refresh is...	10/04/2011
8009501	Storage apparatus and power saving method thereof This storage apparatus includes an access history storage unit for storing, when there is a write request for writing data into the data storage unit or a read request for reading data stored in the data storage unit, history of the write request or read request as ...	08/30/2011
7995418	Method and computer program for controlling a storage device having per-element selectable power supply voltages A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multipl...	08/09/2011
7990796	Energy efficient memory access technique for single ended bit cells A method for conserving power in a device. The method generally includes the steps of (A) generating a polarity signal by analyzing a current one of a plurality of data items having a plurality of data bits, the polarity signal having an inversion bit indicating tha...	08/02/2011
7986584	Memory device having multiple power modes A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the f...	07/26/2011
7978560	Static memory cell having independent data holding voltage A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage n...	07/12/2011
7969814	Read command triggered synchronization circuitry A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe ...	06/28/2011
7961546	Memory power management systems and methods Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a fir...	06/14/2011
7944770	Static random access memory system and control method for static random access memory system A static random access memory system used within a microprocessor includes a static random access memory array including a plurality of static random access memories, a storage unit configured to store a context ID used in the execution of a program or a process in ...	05/17/2011
7920439	Semiconductor memory device using a bandgap reference circuit and a reference voltage generator for operating under a low power supply voltage A semiconductor memory device includes a boosting power supply circuit that boosts a first voltage to a second voltage, which is higher than an external power supply. A first bandgap reference (BGR) circuit operates on the second voltage generated by the boosting po...	04/05/2011
7881151	Memory device having multiple power modes A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the f...	02/01/2011
7864600	Memory cell employing reduced voltage A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the m...	01/04/2011
7859936	Method and apparatus for saving and restoring the state of a power-gated memory device A method and apparatus involving a circuit is disclosed. The circuit has separate first and second portions, where the first portion includes a first memory device such as a flip-flop, and the second portion includes a second memory device such as a latch. The first...	12/28/2010
7852699	Power saving method and circuit thereof for a semiconductor memory A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost p...	12/14/2010
7852700	Memory device A memory device includes a power supply line, a memory cell, a memory cell power supply node provided between the memory cell and the power supply line, a first voltage generating circuit coupled to the memory cell power supply node for supplying the memory cell pow...	12/14/2010
7848172	Memory circuit having reduced power consumption A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory...	12/07/2010
7848171	Semiconductor memory device compensating leakage current A cell array has a plurality of memory cells arranged in a matrix. Each one terminal of a plurality of switching circuits is connected to a bit line. A leakage current compensating circuit has an output node connected in common to the other terminal of the switching...	12/07/2010
7830732	Staged-backup flash backed dram module A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily powe...	11/09/2010
7826304	Simplified power-down mode control circuit utilizing active mode operation control signals A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit...	11/02/2010
7821864	Power management of memory via wake/sleep cycles A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, the...	10/26/2010
7817490	Low-power operation of static memory in a read-only mode A static random access memory (SRAM) operable that is biased at lower power supply voltages in a read-only mode than in a read/write mode. The SRAM can be embedded within a large-scale integrated circuit, for example in combination with a microprocessor and associat...	10/19/2010
7813209	Method for reducing power consumption in a volatile memory and related device A method for reducing power consumption in a volatile memory includes switching off a bitline voltage provider according to a leakage control signal when a bitline array corresponding to the bitline voltage provider is dysfunctional due to a wordline to bitline shor...	10/12/2010
7791976	Systems and methods for dynamic power savings in electronic memory operation Power reduction is accomplished in an electronic memory by segmenting portions of the memory and only enabling certain memory portions depending upon where the memory is to be accessed. In one embodiment, the bit lines are segmented using latch repeaters to control ...	09/07/2010
7791977	Design structure for low overhead switched header power savings apparatus A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the fi...	09/07/2010
7746724	Asynchronous data transmission A method and apparatus for accessing a memory device. The method includes providing control signals for an access command to the memory device via an asynchronous interface and transmitting data for the access command to the memory device. The method also includes e...	06/29/2010
7729192	Circuit and method for reducing power in a memory device during standby modes A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and ...	06/01/2010
7715267	Driving method and driving circuit and low power memory using the same A driving circuit includes a first switch, a first driver and a second driver. The first switch has a first terminal coupled to a first voltage. The first driver includes a second switch and a third switch. The second switch has a first terminal coupled to a second ...	05/11/2010
7706205	Static memory cell having independent data holding voltage A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage n...	04/27/2010
7706206	Semiconductor integrated circuit A semiconductor integrated circuit includes a first buffer and a second buffer having different operational timing, a first voltage power supply for generating a first power supply voltage supplied to the first buffer in accordance with the operational timing of the...	04/27/2010
7692998	Circuit of detecting power-up and power-down A power-up/power-down detecting circuit may include a power detecting circuit, a selecting circuit, and a determining circuit. The power detecting circuit may generate a plurality of detection signals based on a plurality of sensing signals corresponding to currents...	04/06/2010
7692999	Nonvolatile memory and semiconductor device including nonvolatile memory An object is to provide a nonvolatile memory with reduced power consumption. The nonvolatile memory includes a memory element that has a low resistance state and a high resistance state, a writing circuit, a resistance element, a voltage source input terminal that i...	04/06/2010
7684277	Non-volatile memory device with controlled application of supply voltage Embodiments of the invention provide a memory device comprising a non-volatile memory element, a read-out circuit for reading out an item of memory information stored in the memory element, a switching unit, by means of which a supply voltage can be applied to the r...	03/23/2010
7679982	Multi-die packaged device A packaged multi die device includes at least one memory die. The one or more of the memory dice includes a memory function circuit configured to program or read data, a logic circuit configured to control the program operation and the read operation of the memory f...	03/16/2010

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Class 365/227 - Conservation of power