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User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 8098538 | Spin-torque bit cell with unpinned reference layer and unidirectional write current Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conduct... | 01/17/2012 |
| 7940592 | Spin-torque bit cell with unpinned reference layer and unidirectional write current Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conduct... | 05/10/2011 |
| 7929370 | Spin momentum transfer MRAM design We describe the structure and method of formation of a STT MTJ or GMR MRAM cell element that utilizes transfer of spin torque as a mechanism for changing the magnetization direction of a free layer. The critical current is reduced by constructing the free layer as a... | 04/19/2011 |
| 7525862 | Methods involving resetting spin-torque magnetic random access memory with domain wall A method for resetting a spin-transfer based random access memory system, the method comprising, inducing a first current through a first conductor, wherein the first current is operative to propagate a magnetic domain wall in a ferromagnetic film layer and the prop... | 04/28/2009 |
| 7411854 | System and method for controlling constant power dissipation A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of t... | 08/12/2008 |
| 7394683 | Solid state magnetic memory system and method A solid state magnetic memory system and method disposes an array of magnetic media cells in an array on a substrate. In an exemplary embodiment, drive electronics are fabricated into the substrate through conventional CMOS processing in alignment with associated ce... | 07/01/2008 |
| 7372757 | Magnetic memory device with moving magnetic domain walls A magnetic memory device includes a plurality of first metal lines arranged in parallel on a substrate and including a plurality of magnetic domains with variable magnetization directions. A plurality of second metal lines is arranged on the substrate perpendicular ... | 05/13/2008 |
| 7366009 | Separate write and read access architecture for a magnetic tunnel junction A magnetoresistive device is provided with separate read and write architecture. In one embodiment, a magnetic tunnel junction (MTJ) has a nonmagnetic nonconductive barrier layer sandwiched between two ferromagnetic conducting layers. A first read line is coupled to... | 04/29/2008 |
| 7362644 | Configurable MRAM and method of configuration A configurable MRAM device is achieved. The device comprises a memory array of magnetic memory cells. A first part of the array comprises the memory cells that can be accessed for reading and writing during normal operation. A second part of the array comprises the ... | 04/22/2008 |
| 7359235 | Separate write and read access architecture for a magnetic tunnel junction A magnetoresistive device is provided with separate read and write architecture. In one embodiment, a magnetic tunnel junction (MTJ) has a nonmagnetic nonconductive barrier layer sandwiched between two ferromagnetic conducting layers. A first read line having a firs... | 04/15/2008 |
| 7355883 | Magnetoresistance effect element, its manufacturing method, magnetic reproducing element and magnetic memory A magnetoresistance effect element includes a first ferromagnetic layer (1), insulating layer (3) overlying the first ferromagnetic layer, and second ferromagnetic layer (2) overlying the insulating layer. The insulating layer has formed a throu... | 04/08/2008 |
| 7332781 | Magnetic memory with spin-polarized current writing, using amorphous ferromagnetic alloys, writing method for same The invention concerns a magnetic memory, whereof each memory point consists of a magnetic tunnel junction (60), comprising: a magnetic layer, called trapped layer (61), whereof the magnetization is rigid; a magnetic layer, called free layer (63... | 02/19/2008 |
| 7329935 | Low power magnetoresistive random access memory elements Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier ... | 02/12/2008 |
| 7307874 | Methods of operating magnetic random access memory devices including magnets adjacent magnetic tunnel junction structures A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. A... | 12/11/2007 |
| 7298643 | MRAM element A magnetoresistive memory element including a trapped magnetic region and a free magnetic region separated by a barrier layer. The free magnetic region comprises a stacking of at least two antiferromagnetically-coupled ferromagnetic layers, a layer magnetic moment v... | 11/20/2007 |
| 7289365 | Nonvolatile semiconductor memory device in which write and erase threshold voltages are set at levels symmetrical about neutral threshold voltage of cell transistor A semiconductor device includes a memory cell and driver. The memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a c... | 10/30/2007 |
| 7283384 | Magnetic memory array architecture An MRAM device is provided which includes an array of magnetic elements, a plurality of conductive lines configured to set magnetization states of the magnetic elements and circuitry configured to vary current applications along one or more of the conductive lines. ... | 10/16/2007 |
| 7277317 | MRAM architecture for low power consumption and high selectivity The present invention provides a magnetoresistive memory cell (30), comprising a magnetoresistive memory element (31), a first current line (32) and a second current line (33), the first and the second current line (32, 33) crossin... | 10/02/2007 |
| 7256429 | Memory cell with buffered-layer A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a me... | 08/14/2007 |
| 7254054 | Magnetic random access memory and method for manufacturing the same A magnetic random access memory is provided including a substrate, a magnetoresistance element which includes a ferromagnetic layer having an invertible spontaneous magnetization, which varies in resistance according to the direction of the spontaneous magnetization... | 08/07/2007 |
| 7239568 | Current threshold detector A magnetic memory cell write current threshold detector. The magnetic memory cell write current threshold detector includes a first MRAM test cell receiving a write current and sensing when the write current exceeds a first threshold, and a second MRAM test cell rec... | 07/03/2007 |
| 7239570 | Magnetic memory device and method for magnetic reading and writing Disclosed herein are a magnetic memory device and method for storing and retrieving data. The magnetic memory device includes a read disk and a storage disk. The read disk comprises of an array of read heads wherein the individual read head corresponds to a storage ... | 07/03/2007 |
| 7233537 | Thin film magnetic memory device provided with a dummy cell for data read reference Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a different... | 06/19/2007 |
| 7230845 | Magnetic devices having a hard bias field and magnetic memory devices using the magnetic devices A method and system for providing a magnetic memory device are disclosed. The method and system include providing a magnetic element that includes a data storage layer having at least one easy axis in at least a first direction. The method and system also include pr... | 06/12/2007 |
| 7209382 | Magnetic random access memory In a magnetic random access memory (MRAM), setting data which determines the supply/cutoff timing, magnitude, and temporal change (current waveform) of a write word/bit line current is registered in a setting circuit. A write current waveform control circuit generat... | 04/24/2007 |
| 7206220 | MRAM-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at l... | 04/17/2007 |
| 7203129 | Segmented MRAM memory array In one example, an MRAM memory array includes a plurality of word lines, a plurality of bit lines crossing the word lines, and a plurality of first and second diodes, and magnetic tunnel junction memories. Each first diode includes a cathode, and an anode coupled to... | 04/10/2007 |
| 7195927 | Process for making magnetic memory structures having different-sized memory cell layers An exemplary method for making a memory structure having different-sized memory cell layers comprises forming at least two layers of ferromagnetic materials, forming at least one mask layer above the ferromagnetic materials, patterning the at least one mask layer, e... | 03/27/2007 |
| 7193892 | Magnetic switching with expanded hard-axis magnetization volume at magnetoresistive bit ends A magnetoresistive apparatus and method of operation with improved switching characteristics is provided. Switching of a magnetic direction of a magnetic layer of a magnetoresistive bit is promoted by parallel rotation of local magnetic direction of ends of the bit ... | 03/20/2007 |
| 7184302 | Highly efficient segmented word line MRAM array In an MRAM array based on MTJs, the size of segmented word line select transistors and their associated connections become a significant overhead, especially when the operating point is chosen deep along the hard axis of the asteroid curve. This problem has been ove... | 02/27/2007 |
| 7180769 | World line segment select transistor on word line current source side The word line segment select transistor of a segmented word line array is placed on the word line current source side. This eliminates many undesirable effects currently associated with segmented word line MRAM arrays. ... | 02/20/2007 |
| 7173846 | Magnetic RAM and array architecture using a two transistor, one MTJ cell A new magnetic RAM cell device is achieved. The device comprisese, first, a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A reading switch is coupled between the free layer and a reading line. A writing switch is coupled betwee... | 02/06/2007 |
| 7170778 | High speed low power magnetic devices based on current induced spin-momentum transfer The present invention generally relates to the field of magnetic devices for memory cells that can serve as non-volatile memory. More specifically, the present invention describes a high speed and low power method by which a spin polarized electrical current can be ... | 01/30/2007 |
| 7154773 | MRAM cell with domain wall switching and field select An MRAM cell includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship and separated by a non-magnetic tunneling barrier layer. The first magnetic region includes a reference layer having a fixed ma... | 12/26/2006 |
| 7142448 | Method and system for data communication on a chip Methods and apparatuses are disclosed for communicating data on a chip. In one embodiment, the method includes: reading the data value of a memory element utilizing conductors that are electrically coupled to the memory element, and communicating the value read from... | 11/28/2006 |
| 7136298 | Magnetic random access memory array with global write lines A random access memory array includes random access memory elements arranged in a rows and columns. Each row is divided into a plurality of row groups of elements and each column is divided into a plurality of column groups of elements. The elements in each row grou... | 11/14/2006 |
| 7133307 | Resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage su... | 11/07/2006 |
| 7129098 | Reduced power magnetoresistive random access memory elements Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier ... | 10/31/2006 |
| 7129555 | Magnetic memory with write inhibit selection and the writing method for same The invention relates to a magnetic memory with write inhibit selection and the writing method for same. Each memory element of the invention comprises a magnetic tunnel junction (70) consisting of: a magnetic layer, known as the trapped layer (71), ha... | 10/31/2006 |
| 7123506 | Method and system for performing more consistent switching of magnetic elements in a magnetic memory A method and system for programming a magnetic memory is disclosed. The method and system further include turning on a word line current and turning on a bit line current. The word line current is for generating at least one hard axis field. The bit line current is ... | 10/17/2006 |
