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3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 8050127 | Semiconductor memory device A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additi... | 11/01/2011 |
| 7692991 | Semiconductor memory device and method for designing the same A semiconductor memory device includes first and second column selection signal lines, first bit lines being and second bit lines. The first bit lines are associated with the first column selection signal line. The second bit lines are associated with the second col... | 04/06/2010 |
| 7505348 | Balanced and bi-directional bit line paths for memory arrays with programmable memory cells An improved memory system incorporates an array of memory cells that are subjected to minimal location dependent power variations and, optionally, allows for bi-directional random access of millions of bits. The system architecture provides a consistent amount of bi... | 03/17/2009 |
| 7440350 | Semiconductor integrated circuit device A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a com... | 10/21/2008 |
| 7436690 | Flat cell read only memory using common contacts for bit lines and virtual ground lines In a flat cell read only memory, two bit lines or two virtual ground lines share a common contact such that the contact is slightly adjustable in its location for inserting a local metal word line without increasing the layout area to improve the reading speed of th... | 10/14/2008 |
| 7397694 | Magnetic memory arrays A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the ma... | 07/08/2008 |
| 7379366 | Thin film magnetic memory device capable of conducting stable data read and write operations A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provi... | 05/27/2008 |
| 7376032 | Method and apparatus for a dummy SRAM cell A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and second bit line output circuits. The dummy SRAM cell includes the same fir... | 05/20/2008 |
| 7369452 | Programmable cell A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node is electrically connected to a program voltage. During a read mode, ... | 05/06/2008 |
| 7362651 | Using common mode differential data signals of DDR2 SDRAM for control signal transmission A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core hav... | 04/22/2008 |
| 7339811 | Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packi... | 03/04/2008 |
| 7339812 | Stacked 1T-memory cell structure This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the h... | 03/04/2008 |
| 7319623 | Method for isolating a failure site in a wordline in a memory array According to one exemplary embodiment, a method for isolating a failure site in a leaky wordline in a memory array includes dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion, where the initial leaky wordlin... | 01/15/2008 |
| 7313043 | Magnetic Memory Array A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first ... | 12/25/2007 |
| 7310258 | Memory chip architecture with high speed operation A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at lea... | 12/18/2007 |
| 7286424 | Semiconductor integrated circuit device A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mo... | 10/23/2007 |
| 7281094 | Balanced bitcell for a multi-port register file In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in whic... | 10/09/2007 |
| 7274613 | Dynamic random access memory (DRAM) capable of canceling out complementary noise development in plate electrodes of memory cell capacitors A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of a capacitor, a p... | 09/25/2007 |
| 7257011 | Semiconductor memory having twisted bit line architecture A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a fi... | 08/14/2007 |
| 7227768 | Power interconnect structure for balanced bitline capacitance in a memory array According to one exemplary embodiment, a semiconductor die includes a memory core array situated over a substrate, where the memory core array includes a number of bitlines, where the bitlines can be situated in a first interconnect metal layer in the semiconductor ... | 06/05/2007 |
| 7203087 | Fast reading, low consumption memory device and reading method thereof A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row ... | 04/10/2007 |
| 7200063 | Circuitry for a programmable element As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage sour... | 04/03/2007 |
| 7196957 | Magnetic memory structure using heater lines to assist in writing operations The invention includes a stacked magnetic memory structure. The magnetic memory structure includes a stacked magnetic memory structure. The first layer includes a first plurality of magnetic tunnel junctions. A second layer is formed adjacent to the first layer. The... | 03/27/2007 |
| 7193915 | Semiconductor memory device When a command is input to a semiconductor memory device, a sub-threshold current is reduced to a predetermined value corresponding to the command. After the reduction of the sub-threshold current is completed, the semiconductor memory device starts to operate corre... | 03/20/2007 |
| 7139183 | Logical arrangement of memory arrays An aspect of the present invention is a logical arrangement of memory arrays. The logical arrangement includes a plurality of memory arrays deposed in a row-column configuration, a controller coupled to the plurality of memory arrays and at least one power line, at ... | 11/21/2006 |
| 7110319 | Memory devices having reduced coupling noise between wordlines Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver i... | 09/19/2006 |
| 7075834 | Semiconductor integrated circuit device A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mo... | 07/11/2006 |
| 7075816 | Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on th... | 07/11/2006 |
| 7061792 | Low AC power SRAM architecture In a SRAM structure, power consumption is reduced by providing a structure which allows specific memory cells to be selected using word lines and column select lines, and reducing the load on the column address lines by dividing the load into sectors. The dividing i... | 06/13/2006 |
| 7042749 | Stacked 1T-nmemory cell structure This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the h... | 05/09/2006 |
| 7035161 | Semiconductor integrated circuit An I/O interface circuit immediately close to a bank having a plurality of memory cells and an I/O circuit is directly connected to data line pairs via a switching circuit. Another I/O interface circuit is connected to other data line pairs via switching circuits an... | 04/25/2006 |
| 7023743 | Stacked columnar 1T-MTJ structure and its method of formation and operation This invention relates to an array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing de... | 04/04/2006 |
| 7009899 | Bit line precharge signal generator for memory device Disclosed is a bit line precharge signal generator for a memory device, which reduces a resistance component of a signal line by shortening the length of a signal line transferring bit line signals, and reduces an RC time delay. Control signal generator generates a ... | 03/07/2006 |
| 7006372 | Magnetic random access memory In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, ... | 02/28/2006 |
| 6999358 | Semiconductor memory device A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address... | 02/14/2006 |
| 6954391 | Noise resistant small signal sensing circuit for a memory device Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first c... | 10/11/2005 |
| 6954390 | Noise resistant small signal sensing circuit for a memory device Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first c... | 10/11/2005 |
| 6944080 | Dynamic random access memory(DRAM) capable of canceling out complimentary noise developed in plate electrodes of memory cell capacitors A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic mem... | 09/13/2005 |
| 6940748 | Stacked 1T-nMTJ MRAM structure This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher ... | 09/06/2005 |
| 6937495 | Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory ce... | 08/30/2005 |
