Class 365/203 - Precharge

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter wherein circuit lines or elements are charged
No. of patents: 2991
Last issue date: 01/24/2012

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Number	Title	Issue Date
8102725	Method for controlling a pre-charge process and a respective integrated circuit A method of controlling a pre-charge process of a data line (21, 22) in an integrated circuit (100) comprises the step of monitoring a rate of change of a voltage applied to the data line (21, 22) for enhancing the security. Further a respective...	01/24/2012
8089794	Precharge circuits and methods for content addressable memory (CAM) and related devices A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the...	01/03/2012
8077533	Memory and method for sensing data in a memory using complementary sensing scheme In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118	12/13/2011
8050124	Semiconductor memory device and method with two sense amplifiers A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respective...	11/01/2011
8040747	Circuit and method for controlling precharge in semiconductor memory apparatus A circuit for controlling precharge in a semiconductor memory apparatus includes a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signa...	10/18/2011
8040746	Efficient word lines, bit line and precharge tracking in self-timed memory device A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line col...	10/18/2011
8036056	Semiconductor memory device and method of inputting and outputting data in the semiconductor memory device A semiconductor memory device includes a memory cell array and an input/output path circuit. The input/output path circuit performs an input/output line pre-charge operation at a write end time point and outputs data stored in the memory cell array when the semicond...	10/11/2011
8031545	Low read current architecture for memory A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured. ...	10/04/2011
8027213	Mechanism for measuring read current variability of SRAM cells A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to s...	09/27/2011
8027212	Method and apparatus for a dynamic semiconductor memory with compact sense amplifier circuit A high-density dynamic memory device with compact sense amplifier circuit is described. The memory device achieves high density through the use of a compact sense amplifier circuit that employs a single transistor to sense stored dynamic data. Functionality of the d...	09/27/2011
8009495	Memories with front end precharge Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the...	08/30/2011
8009494	Semiconductor memory device implementing full-VDD bit line precharge scheme using bit line sense amplifier A semiconductor memory device using a full-VDD bit line precharge scheme by using a bit line sense amplifier includes a precharge unit precharging a bit line and a complementary bit line from a power voltage to a voltage that is less than the power voltage by a pred...	08/30/2011
8004916	Semiconductor circuit Embodiments relate to semiconductor devices and methods for fabricating semiconductor devices. According to embodiments, a semiconductor device may include a bit line and a bit line bar. The device may also include a precharge controller that may generate a precharg...	08/23/2011
7995410	Leakage and NBTI reduction technique for memory In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and partic...	08/09/2011
7995409	Memory with independent access and precharge Digital memory devices and systems, as well as methods of operating digital memory devices, that include access circuitry to access a first subset of a plurality of memory cells associated with a current access address during a current access cycle and precharge cir...	08/09/2011
7986571	Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being ac...	07/26/2011
7986577	Precharge voltage supplying circuit A precharge voltage supplying circuit comprises a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder c...	07/26/2011
7983102	Data detecting apparatus and methods thereof A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of mem...	07/19/2011
7978551	Bit line equalizing control circuit of a semiconductor memory apparatus A bit line equalizing control circuit of a semiconductor memory apparatus includes a control signal generating unit that receives a bank active signal to generate a control signal such that a bit line equalizing signal is delayed and enabled, a bit line equalizing s...	07/12/2011
7965570	Precharge control circuits and methods for memory having buffered write commands Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit....	06/21/2011
7965569	Semiconductor storage device A voltage of a bit line connected to a memory cell is stepped up up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a st...	06/21/2011
7952946	No-disturb bit line write for improving speed of eDRAM A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit...	05/31/2011
7948820	Circuit pre-charge to sense a memory line Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produ...	05/24/2011
7940589	Bit line sense amplifier of semiconductor memory device and control method thereof A bit line sense amplifier circuit for use in a semiconductor memory device, and a control method thereof, in which the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a sense amplifier enable signal to enable the sense amp...	05/10/2011
7936577	Match line precharge circuits and methods for content addressable memory (CAM) device A content addressable memory (CAM) may include a plurality of precharge circuits, each coupled to a group of CAM cells and comprising a first precharge path that is temporarily enabled in response to an activated first control signal, and a second precharge path tha...	05/03/2011
7936624	Reduced power bitline precharge scheme for low power applications in memory devices A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished with a lower power supply, the second step completes the bitline precharge with the higher power supply. ...	05/03/2011
7929364	Semiconductor memory apparatus Disclosed is a semiconductor memory apparatus capable of improving precharge performance. The semiconductor memory apparatus includes a plurality of memory banks, data input/output lines commonly connected to the memory banks, and a plurality of precharge circuit un...	04/19/2011
7924641	Data flow scheme for low power DRAM Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determ...	04/12/2011
7920434	Memory sensing method and apparatus Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory...	04/05/2011
7916567	Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in ...	03/29/2011
7911862	Latency control circuit and method thereof and an auto-precharge control circuit and method thereof A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock sig...	03/22/2011
7903487	Semiconductor memory device, and method of controlling the same An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circ...	03/08/2011
7894287	Semiconductor memory device controlling a voltage supplied to a dummy bit line The present invention relates to a semiconductor memory device, and more precisely to a semiconductor memory device which controls the voltage supplied to a dummy bit line and a biasing method. The semiconductor memory device includes a dummy bit line disposed in a ...	02/22/2011
7881137	Read assist for memory circuits with different precharge voltage levels for bit line pair A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that th...	02/01/2011
7872932	Method of precharging local input/output line and semiconductor memory device using the method A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell...	01/18/2011
7869292	Dynamic type semiconductor memory device and operation method of the same A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower si...	01/11/2011
7869291	Precharge voltage supply circuit and semiconductor device using the same A precharge voltage supply circuit and a semiconductor device using the same are disclosed. The semiconductor device includes a first comparator for comparing a precharge voltage with a first reference voltage having a first voltage level and outputting a first comp...	01/11/2011
7859926	Semiconductor memory device Disclosed is a semiconductor memory device including a discharge circuit that discharges bit lines to a ground potential, a sense amplifier of a single-ended input configuration, and a charging transistor connected between a power supply and an input node of the sen...	12/28/2010
7852652	Match line precharge circuits and methods for content addressable memory (CAM) device A content addressable memory (CAM) device can include a number of match lines, each coupled to a plurality of CAM cells. The CAM device also includes one or more one precharge circuits. Such a precharge circuit can have a first precharge path that couples a match li...	12/14/2010
7852694	Semiconductor memory device for reducing precharge time A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted throug...	12/14/2010

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Class 365/203 - Precharge