Class 365/201 - Testing

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter including the specifics of the memory which
No. of patents: 4236
Last issue date: 02/07/2012

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Number	Title	Issue Date
8112730	Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical la...	02/07/2012
8111568	Semiconductor memory device having bit test circuit with ignore function A semiconductor memory device including a bit test circuit with an ignore function is provided. The semiconductor memory device includes a memory cell array and a bit test circuit. The memory cell array includes a plurality of memory cells. The bit test circuit is c...	02/07/2012
8107307	Memory device with data paths for outputting compressed data A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression modu...	01/31/2012
8094508	Memory block testing A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of ...	01/10/2012
8094476	Content addressable memory match signal test device and methods thereof A content addressable memory (CAM) of a data processing device can operate in a normal mode or a test mode. In the normal mode, the CAM provides a match value in response to determining that a received data value matches one of a plurality of values stored at memory...	01/10/2012
8085609	Nonvolatile semiconductor memory and method for detecting leakage defects of the same There is provided a nonvolatile semiconductor memory wherein a normal mode voltage is provided to a selected word line when a normal mode is selected, and a test mode voltage lower than the normal mode voltage is provided to the selected word line when a test mode i...	12/27/2011
8085610	SRAM and testing method of SRAM An SRAM includes a memory cell; and a control circuit configured to change a signal level of a signal which is used in an ordinary mode for access to the memory cell in a test mode to apply a disturbance to the memory cell. The control circuit can change the signal ...	12/27/2011
8064279	Structure and method for screening SRAMS An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method ...	11/22/2011
8059479	Test circuit for an unprogrammed OTP memory array Circuits for testing unprogrammed OTP memories to ensure that wordline and bitline connections, column decoders, wordline drivers, correctness of decoding, sensing and multiplexing operate properly. The OTP testing system includes one or both of column test circuitr...	11/15/2011
8059478	Low cost testing and sorting for integrated circuits Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an acti...	11/15/2011
8050122	Fuse apparatus for controlling built-in self stress and control method thereof A fuse apparatus for controlling a built-in self stress unit includes a built-in self stress configured to repeatedly generate any stress test pattern in a test mode, and generate a one-cycle end signal when one cycle for the generated stress test pattern has ended,...	11/01/2011
8050123	Semiconductor memory device and method of defective cell test by adjusting a bitline reference/precharge level A semiconductor memory device simultaneously selects an object cell and a counter cell which connect with a common bit line, simultaneously activates sub-word lines of the object cell and the counter cell after predetermined levels are written in the object cell and...	11/01/2011
8045409	Semiconductor memory device A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, a...	10/25/2011
8045408	Semiconductor integrated circuit with multi test A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/wri...	10/25/2011
8036055	Semiconductor storage device A semiconductor storage device includes: a plurality of I/O terminals configured in a block, and including a representative I/O terminal and a non-representative I/O terminal; a plurality of memory cells each associated with the plurality of I/O terminals to store d...	10/11/2011
8036052	Semiconductor memory device and test method thereof Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, s...	10/11/2011
8036053	Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations...	10/11/2011
8036054	Semiconductor memory device with improved sensing margin A semiconductor memory device includes a signal generating unit for generating first and second enable signals in response to a power-up signal, a first sub-word line signal driving unit for driving a first sub-word line signal in response to the first enable signal...	10/11/2011
8023349	Memory system, memory test system and method of testing memory system and memory test system A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal co...	09/20/2011
8023348	Method and apparatus for testing a memory device Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The metho...	09/20/2011
8023350	Memory malfunction prediction system and method A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value fo...	09/20/2011
8009493	Semiconductor memory apparatus and test method thereof A semiconductor memory apparatus includes a bit line pair electrically connected to a memory cell and a bit line sense amplifier for detecting and amplifying voltage levels of the bit line pair. The semiconductor memory apparatus is configured to perform a test to d...	08/30/2011
8004915	Area-efficient memory built-in-self-test circuitry with advanced debug capabilities for distributed memory blocks An integrated circuit is provided with built-in-self test circuitry. The integrated circuit may have multiple blocks of memory. The memory may be tested using the built-in-self test circuitry. Each memory block may include a satellite address generator that is used ...	08/23/2011
8004914	Method of testing nonvolatile memory device A method includes performing test bit setting; programming a first page using data set by the test bit setting, and storing a fail status bit in a page buffer, which is connected to a first bit line having a fail status, based on a verification result of the test pr...	08/23/2011
8000160	Semiconductor device and cell plate voltage generating apparatus thereof A semiconductor device includes a monitor voltage transfer unit and a voltage generating unit. The monitor voltage transfer unit selects one of a plurality of internal voltages including a cell plate voltage in accordance with a test mode to output it to a voltage m...	08/16/2011
7995408	Circuit for supplying a reference voltage in a semiconductor memory device for testing an internal voltage generator therein A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external reference voltage, a switching unit selectively configured to supply the int...	08/09/2011
7990790	Write driver circuit of PRAM A phase change random access memory (PRAM) has a function of evaluating the lifetime and reliability of a cell in a write driver circuit. The write driver circuit of the PRAM includes a normal driver configured to provide a write current for set or reset of a phase ...	08/02/2011
7990788	Refresh characteristic testing circuit and method for testing refresh using the same A refresh characteristic test circuit is provided, in a recessed semiconductor device, that is capable of verifying whether a refresh failure is caused by the neighbor/passing gate effect or not and a method for testing the refresh characteristic. The refresh charac...	08/02/2011
7990789	Semiconductor memory device and control method A semiconductor memory device, in which a plurality of data output lines are commonly used by a plurality of banks, includes a plurality of gate circuits each of which are provided at each intermediate position of the plurality of the data output lines, and is contr...	08/02/2011
7986156	Semiconductor device including address signal generating protion and digital-to-analog converter An exemplary aspect of an embodiment of the present invention is a semiconductor device including a plurality of test elements formed in an array on a semiconductor substrate, an address signal generating portion that generates an address signal corresponding to eac...	07/26/2011
7965568	Semiconductor integrated circuit device and method of testing same A semiconductor integrated circuit device includes a first chip that is directly accessible from outside, a second chip that transmits and receives data to and from the first chip, the second chip being not directly accessible from outside, and a through circuit tha...	06/21/2011
7961535	Test circuit and method for use in semiconductor memory device A test circuit and method for use in a semiconductor memory device is provided. The test method for use in a semiconductor memory device including a plurality of memory blocks may include sequentially enabling a plurality of word lines by applying a stress to the wo...	06/14/2011
7961537	Semiconductor integrated circuit A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated. ...	06/14/2011
7961536	Memory device and methods thereof A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured t...	06/14/2011
7944765	Programmable logic device with built in self test In one embodiment of the invention, an integrated circuit such as a programmable logic device includes volatile memory, nonvolatile memory, and a data shift register for reading data from the nonvolatile memory and for reading data from and writing data to the volat...	05/17/2011
7940588	Chip testing circuit The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a mu...	05/10/2011
7940584	Method for inspecting the electrical performance of a flash memory cell The present invention discloses a method for inspecting the electrical performance of a flash memory cell, which comprises: performing electron-storage programming on a flash memory cell for a pre-determined period; screening out flash memory cells that reach a spec...	05/10/2011
7940585	Multi-column decoder stress test circuit The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test ci...	05/10/2011
7940587	Semiconductor memory device and test method thereof A semiconductor memory device comprises a memory cell array having memory cells arranged at intersections of word lines and bit lines, a first sense amplifier connected to a bit line at a predetermined position of the bit lines, a second sense amplifier connected to...	05/10/2011
7940586	Semiconductor memory device A semiconductor memory device includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the globa...	05/10/2011

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Class 365/201 - Testing